ismailov-e
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hi.
Let me say i have a 8-bit 9 register, one of them is output. Input wire 8-bit.
This input variable indicates only to use certain number of register. If input is 5 than use only first 5 registers.
For example i have to output first 5 registers each clock cycle.
I know that reg1,reg2 is string and code will not work.
Is there any syntaxis to use certain registers instead
?
Let me say i have a 8-bit 9 register, one of them is output. Input wire 8-bit.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 wire [7:0 ]input1; reg [7:0] rega1 = 1; reg [7:0] rega2 = 2; reg [7:0] rega3 = 3; reg [7:0] rega4 = 4; reg [7:0] rega5 = 5; reg [7:0] rega6 = 6; reg [7:0] rega7 = 7; reg [7:0] rega8 = 8; reg [7:0] st = 0 reg [7:0] out = 0;
This input variable indicates only to use certain number of register. If input is 5 than use only first 5 registers.
For example i have to output first 5 registers each clock cycle.
Code Verilog - [expand] 1 2 3 4 5 6 st <= input1; if (st != 0) begin st <= st - 1; out <= rega[st]; end
I know that reg1,reg2 is string and code will not work.
Is there any syntaxis to use certain registers instead
Code Verilog - [expand] 1 rega[st]