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[SOLVED] Verilog loop with certain registers

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ismailov-e

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hi.
Let me say i have a 8-bit 9 register, one of them is output. Input wire 8-bit.

Code Verilog - [expand]
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wire [7:0 ]input1;
reg [7:0] rega1 = 1;
reg [7:0] rega2 = 2;
reg [7:0] rega3 = 3;
reg [7:0] rega4 = 4;
reg [7:0] rega5 = 5;
reg [7:0] rega6 = 6;
reg [7:0] rega7 = 7;
reg [7:0] rega8 = 8;
reg [7:0] st = 0
reg [7:0] out = 0;


This input variable indicates only to use certain number of register. If input is 5 than use only first 5 registers.
For example i have to output first 5 registers each clock cycle.

Code Verilog - [expand]
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st <= input1;
if (st != 0)
begin
st <= st - 1;
out <= rega[st];
end


I know that reg1,reg2 is string and code will not work.
Is there any syntaxis to use certain registers instead

Code Verilog - [expand]
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rega[st]

?
 

ads-ee

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Use an array of registers:

Code Verilog - [expand]
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reg [7:0] rega [1:9];
//then this works:
rega[st] <= 1;
//and
out <= rega[st];
//also works

 

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ismailov-e

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Use an array of registers:

Code Verilog - [expand]
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reg [7:0] rega [1:9];
//then this works:
rega[st] <= 1;
//and
out <= rega[st];
//also works

Cool man!!. Once i saw such syntax, but did't know what is mean.
Thanks ads-ee.
 

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