verilog initial and always block

[preethi19]

i'm starting to learn verilog and in behavioral modelling was done within 2 procedural blocks which were initial and always... It was put "Initial blocks are usually used to initialize variables and to describe stimulus waveforms which exercise which drive the simulation.
An always block continuously repeats its execution during a simulation. Always blocks usually contain behavioral code that models the actual circuit operation"

but it was also put that initial and always blocks are separate (like not dependent on each other)

my doubt is how can we describe circuit only with always block... don't we need the initial block to initialize the variable values which will be used in the always block... i mean so they are dependent right... sorry if i am wrong... i'm bit confused

 

[arishsu]

initial blocks are usually used for simulation. You can use initial blocks both in test bench and main code, but initial blocks are not synthesisable; that means you cannot run that code on FPGA.

Unlike always block, initial blocks only run once in code execution. It's not necessary that you have to provide initial values to the variables. Those variables will be read as 'x' or unconnected. Or you can define those variables in the always block or in main code.
For example: y=in ? 2'b10 : 2'bzz; That is, the variable y will have value 10 if in=1, otherwise the value of y will always be zz