Verilog: Illegal reference to net

[cmkastn]

I'm a VHDL guy, and right now I'm working on someone else's verilog. I'm trying to initialize a memory to all 0's for simulation purposes, and I keep getting an error:

Illegal reference to net "k".

Here's the code:

      reg [data_bits-1:0] main_memory_0 [0:mem_sizes];
      reg [data_bits-1:0] main_memory_1 [0:mem_sizes];
      reg [data_bits-1:0] main_memory_2 [0:mem_sizes];
      reg [data_bits-1:0] main_memory_3 [0:mem_sizes];

   initial
     begin
	for(k = 0; k < mem_sizes; k = k + 1)
	  begin
	     main_memory_0[k] = {data_bits{1'b0}};
	     main_memory_1[k] = {data_bits{1'b0}};
	     main_memory_2[k] = {data_bits{1'b0}};
	     main_memory_3[k] = {data_bits{1'b0}};
	  end
     end

Any hints would be much appreciated.

 

[rberek]

Declare"k" as an integer and try that.

r.b.

 

[kalyansumankv]

if u want to initialise the memory only for simulation purpose means,
there will be an option in the simulation tool itself for loading some initial value.
for modelsim:
view-> memory->select an item -> right click for import data pattens -> and fill the required data..

hope this will solve ur prob..

 

[mux_master]

Your declaration of "k" is most likely incorrect. Try making it a reg [31:0] or an int like another poster suggested. The error you have makes me think you have it declared as a wire.