cmkastn
Newbie level 3
I'm a VHDL guy, and right now I'm working on someone else's verilog. I'm trying to initialize a memory to all 0's for simulation purposes, and I keep getting an error:
Illegal reference to net "k".
Here's the code:
Any hints would be much appreciated.
Illegal reference to net "k".
Here's the code:
Code:
reg [data_bits-1:0] main_memory_0 [0:mem_sizes];
reg [data_bits-1:0] main_memory_1 [0:mem_sizes];
reg [data_bits-1:0] main_memory_2 [0:mem_sizes];
reg [data_bits-1:0] main_memory_3 [0:mem_sizes];
initial
begin
for(k = 0; k < mem_sizes; k = k + 1)
begin
main_memory_0[k] = {data_bits{1'b0}};
main_memory_1[k] = {data_bits{1'b0}};
main_memory_2[k] = {data_bits{1'b0}};
main_memory_3[k] = {data_bits{1'b0}};
end
endAny hints would be much appreciated.