[SOLVED] Verilog if statment syntax.

ismailov-e · Feb 12, 2015

Hi everybody!
I have this part of code:

Code:

if (write_pointer <= NUMBER_OF_INPUT_WORDS-1)

How can i understand this syntax?
Is it mean that "write_pointer" is taking value of " NUMBER_OF_INPUT_WORDS-1" by the way it is checking equality?

FvM · Feb 12, 2015

It's a relational operator "less than or equal".

ismailov-e · Feb 13, 2015

FvM said:
It's a relational operator "less than or equal".

Relational operator like in C.

Thanks FvM.