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Verilog HDL2x1 MUX design

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vickyuet

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Dear All,

I had written verilog HDL behavioral code for 4 bit 2x1 mux but my requirement is that i want a generalized code so that i can call it from top level module based upon width of my data.

I want that mux code to behave as 4-bit wide 2X1 mux or on requirement 8-bit wide 2x1 mux as well in same design.Any suggestion how can i adjust this bit width problem in verilog.One way is to call that 4-bit wide 2x1 mux twice to get functionality of 8-bit wide 2x1 mux but i do not want that.Actually my requirement in a design is to use 4 bit 2X1 mux as well as 8-bit 2X1 mux that i intend 2 implement from a general n-bit 2x1 mux.

regards
 

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