* Verilog HDL error at *: declaring global objects is a System verilog feature

[manili]

Hi all,
I'm using Quartus II to compile a verilog code.
You can imaging the code as below :

File1.v:

reg A, B, C;
wire D, E, F;

task My_Task;
//use A, ..., F here.
endtask
----------------------------
File2.v:

module Top;
`include "File1.v"
//use My_Task here
endmodule
----------------------------

But the compiler does not compile my code and give me this error :

Error (error id): Verilog HDL error at File1.v(some line): declaring global objects is a SystemVerilog feature

Please correct me if I'm wrong:
The precompiler program should append File1.v into File2.v at the place that you write "`include "File1.v"". So there should be no problem with the code because it's just like to pass the following to the compiler :

----------------------------
File2.v:

module Top;
reg A, B, C;
wire D, E, F;

task My_Task;
//use A, ..., F here.
endtask

//use My_Task here
endmodule

Thank you very much for your help.