Verilog HDL - Altera Related Tips and Recommendations

[bigdogguru]

Please post any tips and recommendations concerning the synthesis of Verilog designs.

Hardware Description Language (HDL) coding style recommendations to ensure optimal synthesis results when targeting Altera® devices:

Recommended HDL Coding Styles

 

[bigdogguru]

Altera provide example cores and instructions for implementing functions using Verilog HDL.

A nice assortment of cores with good documentation, everything from adders/subtrators to SDRAM interfaces.

Verilog Core Examples

 

[bigdogguru]

This tutorial explains how to use the SignalTap II feature within Altera’s Quartus software using Verilog Designs and DE2 Development Board.

The SignalTap II Embedded Logic Analyzer is a system-level debugging tool that captures and displays signals in circuits designed for implementation in Altera’s FPGAs.

**broken link removed**

 

[bigdogguru]

A step by step guide demonstrating how to use Altera’s Quartus II software to Synthesis and upload Verilog code for the Cyclone II demonstration boards.


Altera Verilog DE2 Guide Microsoft Office Word Format (.doc)

 

[bigdogguru]

This tutorial presents an introduction to Altera’s SOPC Builder software, which is used to implement a system that uses the Nios II processor on an Altera FPGA device.

The system development flow is illustrated by giving step-by-step instructions for using the SOPC Builder in conjuction with the Quartus software to implement a simple system.

**broken link removed**

 

[bigdogguru]

Verilog, and the Altera Environment Tutorial

Tutorial Includes:

1. Create a new Project
2. Write your Serial Transceiver Code
3. Pin Assignment
4. Code Compilation
5. Simulating the Designed Circuit
6. Programming and Configuring the FPGA Device

 

[bigdogguru]

Forrest Heller's Implementation of SHA1 in Verilog on an Altera DE2

Forrest Heller --

SHA1 is a cryptographically secure hash function in widespread use. It takes data (commonly known as the "message") and produces a 40-byte hash ("digest") that is unique to every message. You can know a hash for a given message, but you can't know a message for a given hash--it takes too much computing power.

A very nice implementation and development discussion, worth checking out.

 

[bigdogguru]

**broken link removed**

An effective way of determining the correctness of a logic circuit is to simulate its behavior. This tutorial provides an introduction to such simulation using Altera’s University Program Simulator, called Qsim.

 

[bigdogguru]

Using the SDRAM Memory on Altera’s DE2 Board with Verilog Design

This tutorial explains how the SDRAM chip on Altera’s DE2 Development and Education board can be used with a Nios II system implemented by using the Altera SOPC Builder. The discussion is based on the assumption that the reader has access to a DE2 board and is familiar with the material in the tutorial Introduction to the Altera SOPC Builder Using Verilog Design.

 

[bigdogguru]

Tutorial of ALTERA Cyclone II FPGA Starter Board with Verilog

 

[bigdogguru]

This paper addresses the issues of design considerations for efficient resource allocation for FPGA demo-board based digital design laboratories. The paper is organized as follows; section 2 introduces the hardware and software interface features of Altera DE-2 board. Section 3 gives details of incorporating Altera DE-2 into several computer engineering courses, and section 4 gives conclusion of the paper.

**broken link removed**