vlsi_freak
Full Member level 2
verilog generic
Hi All,
I have an input port to a module which is 5 bits say Inp_A[4:0]. Now the number of such inputs depends on a generic parameter say Gen_Nm.
How can i declare such an input ports in my module.
I have tried
Input [4:0][Gen_Num-1 : 0] Inp_A; &
Input [Gen_Num-1 : 0][4:0] Inp_A; &
Input [Gen_Num-1 : 0] Inp_A[4:0]; &
Input [4:0] Inp_A[Gen_Num-1 : 0];
All these seems to be giving compile error.
Please help me, how to go about this
regards,
freak
Hi All,
I have an input port to a module which is 5 bits say Inp_A[4:0]. Now the number of such inputs depends on a generic parameter say Gen_Nm.
How can i declare such an input ports in my module.
I have tried
Input [4:0][Gen_Num-1 : 0] Inp_A; &
Input [Gen_Num-1 : 0][4:0] Inp_A; &
Input [Gen_Num-1 : 0] Inp_A[4:0]; &
Input [4:0] Inp_A[Gen_Num-1 : 0];
All these seems to be giving compile error.
Please help me, how to go about this
regards,
freak