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Verilog Generic Input ports

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vlsi_freak

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verilog generic

Hi All,

I have an input port to a module which is 5 bits say Inp_A[4:0]. Now the number of such inputs depends on a generic parameter say Gen_Nm.

How can i declare such an input ports in my module.
I have tried
Input [4:0][Gen_Num-1 : 0] Inp_A; &
Input [Gen_Num-1 : 0][4:0] Inp_A; &
Input [Gen_Num-1 : 0] Inp_A[4:0]; &
Input [4:0] Inp_A[Gen_Num-1 : 0];

All these seems to be giving compile error.

Please help me, how to go about this

regards,
freak
 

bharat_in

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verilog generic parameters

First of all Verilog does not support more than one dimensional ports declaration.

You can use define, but you will have to specify it at compile time. You can not change it run time(h/w can not reduce/generate at run time :D).
If you want different number of ports, then you will have to change the define and compile again. But this will only work for one dimensional port.
 

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