lastguy
Newbie level 3
In Linux we can use ## to pull in a string and use it as a function name, now I want to do with module name in verilog.
I want instantiating say four modules of mx(x=0~3), each instance uses a different module mmx to further instantiating mmy(y=0~1), so:
mx m0() shall contain: mm0 mm00(); mm0 mm01();
mx m1() shall contain: mm1 mm10(); mm1 mm11();
mx m2() shall contain: mm2 mm20(); mm2 mm21();
mx m3() shall contain: mm3 mm30(); mm3 mm31();
Many thanks for your help.
I need such things because each mmx is a memory of same size/structure, but different contents. I use Xilinx v5 .COE to initial them. Files are long and not sure easier way to initial them. Many thanks!
I want instantiating say four modules of mx(x=0~3), each instance uses a different module mmx to further instantiating mmy(y=0~1), so:
mx m0() shall contain: mm0 mm00(); mm0 mm01();
mx m1() shall contain: mm1 mm10(); mm1 mm11();
mx m2() shall contain: mm2 mm20(); mm2 mm21();
mx m3() shall contain: mm3 mm30(); mm3 mm31();
Many thanks for your help.
I need such things because each mmx is a memory of same size/structure, but different contents. I use Xilinx v5 .COE to initial them. Files are long and not sure easier way to initial them. Many thanks!