Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Verilog Generate statement to declare a `define

Status
Not open for further replies.

viju

Member level 4
Joined
Nov 26, 2006
Messages
71
Helped
16
Reputation
32
Reaction score
9
Trophy points
1,288
Location
Bangalore
Activity points
1,815
Hi,

here is my pseudo code...

"

`timescale 1ns/1ns
module test();
reg a;
reg b;
parameter text1 = 1'b0;

generate
if(text1 === 1'b1)
begin
`define ONE1
initial
$display("\n\n%m : LOOP ONE....\n\n ");
end
endgenerate

generate
if(text1 === 1'b0)
begin
`define ZERO1
initial
$display("\n\n%m : LOOP ZERO...\n\n ");
end
endgenerate

always @(posedge a)
begin
`ifdef ONE1
$display(" ONE IS DEFINED by module %m ");
`endif
end

always @(posedge b)
begin
`ifdef ZERO1
$display(" ZERO IS DEFINED by module %m ");
`endif
end

initial
begin
a = 1'b0;
b = 1'b0;
#5;
a =1'b1;
b =1'b1;
#50 $finish;
end
endmodule


"

and here is its output in vcs and ncverilog

"
test : LOOP ZERO...


ONE IS DEFINED by module test
ZERO IS DEFINED by module test
"

Also clubbed a generate blocks.. but it gives the same result... also clubbed a always block but same result...

can any one help me how to solve this problem? If during generate statement only one generate condition is encountered, the why both the `defines are declared ?
Shouldn't be only one `define should be present in the simulation?

Pl help... looks very strange to me?
Am i missing any thing?
 

billylee

Junior Member level 1
Joined
Sep 10, 2009
Messages
17
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Korea
Activity points
1,390
hi, viju
I've never seen something like this code.
your code has 2 definition, 1 is parameter, 1 is interactive `define.
and u combined it.
how about change parameter to `define text1
and `ifdef text1 `define ONE1

and also there is no reason to define dual clock.
have a good day~ :)
 

denki23

Junior Member level 3
Joined
Sep 16, 2008
Messages
25
Helped
7
Reputation
14
Reaction score
2
Trophy points
1,283
Activity points
1,426
I'm not %100 positive, but i'm pretty sure that compiler directives (like `define) get handled in a preprocessing step analogous to #define macros in C. if that is the case then the preprocessor is only looking for compiler directives and could care less about the other Verilog language constructs.

Added after 1 minutes:

Also, just out of curiosity, what do you mean by "clubbed"?
 

jassen

Newbie level 6
Joined
Jul 15, 2010
Messages
13
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Location
Chengdu,China
Activity points
1,334
I believe that you should not use the define but variance.
Because define is just active on compile phase, But you need active in running.

You can try replace the `define with variance.
 

cvc

Member level 3
Joined
May 11, 2009
Messages
58
Helped
4
Reputation
8
Reaction score
3
Trophy points
1,288
Location
Bangalore India
Activity points
1,697
`define is pre-processor directive, hence gets expanded before the elab stage - i.e. when the generates are handled.

If you explain your requirements, maybe we can help out with better code. Perhaps you need a simple variable set by generate during elab stage?

Regards
TeamCVC
www.cvcblr.com/blog
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top