Verilog Function Vs Task

[uditkumar1983]

Hi Friends,
There is a lot of difference between function and task and generally we will tell combinational circuit will be designed using function and sequential circuit using task, but task can also be used for combinational circuit ,So My dobut is if task can be used in place of Function so Why specially function required ??means what special features is in function which is not available in task??
as I know these two features in function signed and constant function is available in function but not in task ?? If I am wrong then Please correct me .....

Regards

 

[no_mad]

Hi,

In my opinion, I would say task n function is something like "assign" and "always" in verilog.

Why? For example, we can model combinational circuit using both statement (assign or always).

But why we still need assign then. I think it is still the same reason why we still have "function".

As for me, the rule of thumb is I always use "function" for modeling combinational logic. Most of the time I used "task" in my test bench.

Anyway, this is my personal opinion. Perhaps, other experts can share some thought.

Hope it helps.

 

[smrjaved]

One major difference in function and task is that function simulates in zero simulation time while task can include delays in simulation. thats why combinational block simulation is done using a function. The sequential circuit should also be capable of handling delays. so task is prefered. Remember these can only be used in simulation purposes and not in synthesis as tasks are not synthesizable.

 

[ameed]

hi

same as c language function and task:idea:



thanx.....

 

[vizpal]

Functions --> Consume no Time
Tasks --> Consume Time

 

[yogini]

Differences between Functions and Tasks....
 Functions
 Can enable (call) just another function (not task)
 Execute in 0 simulation time
 No timing control statements allowed
 At least one input
 Return only a single value
 Tasks
 Can enable other tasks and functions
 May execute in nonzero simulation time
 May contain any timing control statements
 May have arbitrary input, output, or Inout
 Do not return any value