Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] verilog function in condition expression of for statement

Status
Not open for further replies.

rainly

Newbie level 1
Joined
Jan 18, 2011
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,289
Hi all,
I have a rookie question. I did the following code:

module adder #(parameter width=8)
....
for(i=0;i<log2(width);i=i+1)
.....

function integer log2;
input [31:0] value;
for(log2 = 0; value > 1; log2 = log2 + 1)
value = value >> 1;
endfunction
endmodule

I get the following error during elaboration:
Error-[V2KGEUV] Unknown or bad value for genvar
Elaboration time unknown or bad value encountered for generate for-statement condition expression.
Please make sure it is elaboration time constant.

Is it correct to use function in the condition expression of for loop?
Is it possible to solve the problem without adding another parameter for log2(width)?
Thank you in advance
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top