Verilog FPGA Encoder and Decoder

[Bwargh]

Hello all,

I'm brand new to Verilog and hardware design all together. I've recently purchased the Nexy2 (Spartan3e) Board. I'm having trouble on how to approach the code portion of writing decoder and encoder modules as well as the module that will instantiate them together. I'm attempting to get this code to display on my board through the board as well.

Right now the only thing I have completed is (and I'm going to assume it's wrong) :

---

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module decoder (s, y);
input [2:0] s;
output [7:0] y;
wire [7:0] y;
 
assign y =
  (s == 3'b000)  ?  8'h01 :
  (s == 3'b001)  ?  8'h02 :
  (s == 3'b010)  ?  8'h04 :
  (s == 3'b011)  ?  8'h08 :
  (s == 3'b100)  ?  8'h10 :
  (s == 3'b101)  ?  8'h20 :
  (s == 3'b110)  ?  8'h40 :
  (s == 3'b111)  ?  8'h80 :
                            8'bx;
 
endmodule

---

Help much appreciated. I'm really hoping to learn this.


Thanks.

 

[joelby]

What exactly are you trying to encode and decode? Do you just want to, say, connect three switches as inputs, and use the eight LEDs as outputs?

I don't see any particular problem with your code (does it synthesise? does it work?) though I find the Verilog case statement easier to read.

 

[Bwargh]

Yeah, three switches will count as the inputs and the LED's will be the eight outputs. So I've done some more (renamed variables in decoder as well).
So far I have :

---

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module decoder(dIN, dOUT
    );
input  [2:0] dIN;
output [7:0] dOUT;
wire [7:0] dOUT;
assign dOUT =
    (dIN == 3'b000) ? 8'h01 :
    (dIN == 3'b001) ? 8'h02 :
    (dIN == 3'b010) ? 8'h04 :
    (dIN == 3'b011) ? 8'h08 :
    (dIN == 3'b100) ? 8'h10 :
    (dIN == 3'b101) ? 8'h20 :
    (dIN == 3'b110) ? 8'h40 :
    (dIN == 3'b111) ? 8'h80 :
                        8'bx;
endmodule

---

for my decoder and..for my encoder:

---

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module encoder(eIN, eOUT
    );
input [7:0] eIN;
output [2:0] eOUT;
wire [2:0] eOUT;
assign eOUT =
    (eIN == 8'h01) ? 3'b000 :
    (eIN == 8'h02) ? 3'b001 :
    (eIN == 8'h04) ? 3'b010 :
    (eIN == 8'h08) ? 3'b011 :
    (eIN == 8'h10) ? 3'b100 :
    (eIN == 8'h20) ? 3'b101 :
    (eIN == 8'h40) ? 3'b110 :
    (eIN == 8'h80) ? 3'b111 :
                        3'bx;
endmodule

---

if these two are correct, my new problem is creating the top module that will instantiate the encoder and decoder modules that will interconnect them with the addition of inverters on the outputs.

 

[joelby]

You haven't quite described how you want to connect the encoder and decoder together, but your top module might look something like

module topmodule (
  input wire [2:0] switches,
  output wire [2:0] leds
);

wire [7:0] encoded_data;
wire [2:0] decoded_data;
encoder enc (
  .dIN(switches),
  .dOUT(encoded_data)
);

decoder dec (
  .dIN(encoded_data),
  .dOUT(decoded_data)
);

assign leds = ~decoded_data; // invert output

endmodule

 

[Bwargh]

I was also provided with the testbench:

timescale 1ns/1ns

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module DecEnc_tb;
 
reg [2:0] in;
wire [2:0] out;
integer  i;
 
//instantiate the DUT
 
DecEnc DecEnc(.in(in), .out(out));
 
//create the stimulus
 
initial begin
   in = 0;
   i =   0;
 
for (i=0; i<B; i=i+i)
 #100 in = i[2:0];
 
end
 
endmodule

---

appreciating the feedback

 

[joelby]

You shouldn't have too much trouble with that test bench, since it's pretty simple, except for these things:

• You previously named the ports dIN and dOUT, and this test bench is expecting them to be called in and out
• Your module was called decoder and the test bench is expecting DecEnc
• The value of B is not defined
• Your decoder expects a 3-bit input and emits an 8-bit output, which doesn't match what the test bench declares, but that could be because the test bench is testing an encoder connected to a decoder (which should theoretically emit the input value, if the operation is symmetric)