Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Verilog examples of how to implement a master/slave SPI

Status
Not open for further replies.

bb12mpc

Newbie level 5
Joined
Mar 15, 2006
Messages
8
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,336
Master/Slave SPI

Is there any example or source verilog for how to implement a master/slave SPI? Thanks!
 

liu_uestc

Junior Member level 1
Joined
Aug 24, 2005
Messages
16
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,367
Master/Slave SPI

i have write one but just have master mode ;because i don't need slave mode;give me some money i do for you !just a little .ok?
 

o0vvv0o

Newbie level 3
Joined
May 18, 2005
Messages
3
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,300
Re: Master/Slave SPI

it that SPI need Money ? We usually send it free in 8 bit mode
 

RegUser_2

Full Member level 2
Joined
Dec 24, 2001
Messages
125
Helped
11
Reputation
22
Reaction score
9
Trophy points
1,298
Activity points
1,507
Re: Master/Slave SPI

bb12mpc said:
Is there any example or source verilog for how to implement a master/slave SPI? Thanks!

Here, enjoy

(And it's free. I believe that one who ask money for help should leave this forum)
 

theHermes

Newbie level 6
Joined
Mar 13, 2011
Messages
13
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,434
hey, I cant see the code now. can someone help me by reposting the code if possible.
thanks a lot!!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top