Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

verilog error Multiple words referenced for memory Variable

Status
Not open for further replies.
A

Alka Arora

Newbie level 6
Joined
Jan 30, 2009
Messages
12
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,354
Hi,

I have declared a reg as reg [63:0] data_vec[0:4];

I am getting parsing error Multiple words referenced for memory Variable

How can I make one signal of 5*64 ,so that this error does not come?


Thanks
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top