verilog error expecting endmodule found if

[vveerendra]

module disp1(A,P,Q,K,CLK,bclock,bclocko);
input [3:0]P;
input [3:0]Q;
output [3:0]K;
input CLK;
output [6:0]A;
reg [6:0]A;
reg [3:0]K;
output bclock;
output bclocko;
reg bclock;
reg bclocko;
integer count=0;
integer counto=0;
if (bclock)
begin
K <= 4'b1110;
case(P)
0:A<=7'b0000001;
1:A<=7'b1001111;
2:A<=7'b0010010;
3:A<=7'b0000110;
4:A<=7'b1001100;
5:A<=7'b0100100;
6:A<=7'b0100000;
7:A<=7'b0001111;
8:A<=7'b0000000;
9:A<=7'b0001100;
endcase
end
else
begin
K<=4'b1101;
case(Q)
0:A<=7'b0000001;
1:A<=7'b1001111;
2:A<=7'b0010010;
3:A<=7'b0000110;
4:A<=7'b1001100;
5:A<=7'b0100100;
6:A<=7'b0100000;
7:A<=7'b0001111;
8:A<=7'b0000000;
9:A<=7'b0001100;
endcase
end
always @(posedge CLK)
if (count < 42666) count = count+1;
else
begin
bclock <= !bclock;
count=0;
end
endmodule

/*ERROR:line 15 expecting 'endmodule', found 'if'
how to fix the error*/

 

[rca]

Well the if need to be in a process,"assign(*)"

 

[dave_59]

Try this

module disp1(
  output reg [6:0] A,
  input [3:0] P,
  input [3:0] Q,
  output reg [3:0] K,
  input CLK,
  output reg bclock,
  output reg bclocko
);
integer count=0;
integer counto=0;
always @(bclock or P or Q)
  if ( bclock ) begin
      K = 4'b1110;
      case(P)
        0:A=7'b0000001;
        1:A=7'b1001111;
        2:A=7'b0010010;
        3:A=7'b0000110;
        4:A=7'b1001100;
        5:A=7'b0100100;
        6:A=7'b0100000;
        7:A=7'b0001111;
        8:A=7'b0000000;
        9:A=7'b0001100;
      endcase
    end
  else
    begin
        K=4'b1101;
        case(Q)
           0:A=7'b0000001;
           1:A=7'b1001111;
           2:A=7'b0010010;
           3:A=7'b0000110;
           4:A=7'b1001100;
           5:A=7'b0100100;
           6:A=7'b0100000;
           7:A=7'b0001111;
           8:A=7'b0000000;
           9:A=7'b0001100;
        endcase
     end
always @(posedge CLK)
    if (count < 42666) 
        count <= count+1;
    else
      begin
        bclock <= !bclock;
        count=0;
      end
endmodule

 

[vveerendra]

Try this

module disp1(
  output reg [6:0] A,
  input [3:0] P,
  input [3:0] Q,
  output reg [3:0] K,
  input CLK,
  output reg bclock,
  output reg bclocko
);
integer count=0;
integer counto=0;
always @(bclock or P or Q)
  if ( bclock ) begin
      K = 4'b1110;
      case(P)
        0:A=7'b0000001;
        1:A=7'b1001111;
        2:A=7'b0010010;
        3:A=7'b0000110;
        4:A=7'b1001100;
        5:A=7'b0100100;
        6:A=7'b0100000;
        7:A=7'b0001111;
        8:A=7'b0000000;
        9:A=7'b0001100;
      endcase
    end
  else
    begin
        K=4'b1101;
        case(Q)
           0:A=7'b0000001;
           1:A=7'b1001111;
           2:A=7'b0010010;
           3:A=7'b0000110;
           4:A=7'b1001100;
           5:A=7'b0100100;
           6:A=7'b0100000;
           7:A=7'b0001111;
           8:A=7'b0000000;
           9:A=7'b0001100;
        endcase
     end
always @(posedge CLK)
    if (count < 42666) 
        count <= count+1;
    else
      begin
        bclock <= !bclock;
        count=0;
      end
endmodule

thank you for your help