Verilog equivalent for Generate, Generics in Vhdl

[vlsi_freak]

verilog 2005 generate

Hi All,

In VHDL, we can remove unwanted logics based on generics using "Generate" construct. How we can do the same in Verilog since Verilog does not have a Generate construct.

Also, what is the equivalent construct in Verilog for Generics in Vhdl.

Please share your thoughts,

regards,
freak

 

[vikas_33]

Verilog Generate

Parmeter is equivalent of genric in verilog ..'

Using generate statement: Verilog 2001 generate statement allow to either instantiating multiple modules without typing them so many times or instantiating modules conditionally. You can use if-else to conditionally instantiate the modules. Also, if you want to instantiate the same module multiple times then better use for loop. This will save you lot of time.

generate for (i=0; i < width; I = i+1) begin

and_or inst1 (out1, in1, in2);

end endgenerate

 

[aji_vlsi]

Re: Verilog Generate

Parmeter is equivalent of genric in verilog ..'

Using generate statement: Verilog 2001 generate statement allow to either instantiating multiple modules without typing them so many times or instantiating modules conditionally. You can use if-else to conditionally instantiate the modules. Also, if you want to instantiate the same module multiple times then better use for loop. This will save you lot of time.

generate for (i=0; i < width; I = i+1) begin

and_or inst1 (out1, in1, in2);

end endgenerate

And in Verilog 2005 and SV 2009, the generate in this context is optional as a for loop outside procedural will be interpreted as generate for.

HTH
Ajeetha, CVC
www.cvcblr.com