Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

verilog doubt clarification

Status
Not open for further replies.
S

sai685

Junior Member level 2
Joined
Sep 4, 2015
Messages
23
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
292
The input variable port "wdata" of module "fifo_top_tb" cannot be driven. what does it mean . please can anyone clarify it.
 

A testbench module shouldn't have ports and thus no input variable.
 
  • Like
Reactions: sai685

    S

    sai685

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top