Verilog Debouncer for a Counter

[eddie_b]

Hi everyone, I'm trying to build a debouncer for an 8-bit counter that registers how many times the button is pushed that differentiates between a full push and release and the button being held down. In other words, the output should be the "clean" number of times the button was fully pushed and released. I also want to include a reset. At the moment, I'm a bit stuck and I don't know what to do. I'm also unable to test it at the moment because I have to be at home all day today. Would anyone please be able to give me some advice for the code I have? Would this code work?

module debouncer(clock, reset, bounce, y);

	input clock;
	input reset;
	input bounce;
	output reg [7:0] y;
	
	reg bounce;
	reg value;
	reg [32:0] counter;
	parameter delay = 50000;

 always @ (posedge btn or posedge rst)
	begin
	
	   if (bounce)
		begin
			if (bounce != value)
			   begin
			   	value <= bounce;
				counter <= 32'b0;
			   end

	     		else if (counter = = delay)
			   begin
				y <= value;
			   end
			else
			   begin
				counter <= counter + 1'b1;
			   end
	      end


		if (reset)
			begin
			y <= 1'b0;
		end
	end
	
endmodule

Thank you, so greatly appreciate it.

 

[FvM]

Definitely not the right way. The counter can't work at all in a level triggered (asynchronous) always block.

Think about a synchronous design based on the clock input. After synchronizing the button input in a register chain, count it#s high and low states, etc.

 

[eddie_b]

What about something like this that uses the positive edge of the clock? Would this work?

module debouncer(clock, bounce, y)

input clock, bounce;
output reg[7:0] = y;

reg[29:0] delay = 0;

assign y = (delay >= 500000)

always @ (posedge clock or posedge reset) begin
	if (bounce)
		if (delay <= 500000)
			delay <= delay + 1;
		else
		    	delay <= delay;
		else begin
			delay <= 0;
		end
	if (reset)
		y <= 1'b0;
	end
end

endmodule

It assigns the output y to the delay and waits for the delay to count up before outputting.

 

[FvM]

That's much better. But it's important to synchronize the bounce input to the clock, preferably in double registers.
e.g.

bounce_s1 <= bounce;
bounce_s2 <= bounce_s1;
if (bounce_s2)

Otherwise the delay counter might jump to unexpected values if the bounce input changes in the setup- and hold window of the counter FFs.

It's also mandatory to make the asynchronous reset mutual exclusive to clock action:

always @(posedge clock or posedge reset)
if (reset)
  begin
  end
else
  begin
  end