This code:
Code Verilog - [expand] |
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| module top;
real a;
real b;
initial begin
a = 3.3;
a = a/2.0;
$display("%f",a);
b = 3.7;
b = b/2;
$display ("%f",b);
$display ("%f", 1000000000000.0/3);
end
endmodule |
gives the following results:
Aldec Riviera Pro 2015.06
# KERNEL: 1.650000
# KERNEL: 1.850000
# KERNEL: 333333333333.333313
# KERNEL: Simulation has finished. There are no more test vectors to simulate.
exit
# VSIM: Simulation has finished.
Icarus Verilog 0.9.7
1.650000
1.850000
333333333333.333313
GPL Cver 2.12a
1.650000
1.850000
333333333333.333313
0 simulation events and 0 declarative immediate assigns processed.
7 behavioral statements executed (1 procedural suspends).
Times (in sec.): Translate 0.0, load/optimize 0.1, simulation 0.1.
End of GPLCVER_2.12a at Fri Nov 11 15:52:38 2016 (elapsed 0.0 seconds).
Veriwell 2.87 (note does not work on last number due to > 32-bit)
1.650000
1.850000
0 Errors, 0 Warnings, Compile time = 0.0, Load time = 0.0, Simulation time = 0.0
Normal exit
Thank you for using Veriwell
Didn't test VCS or Incisive as I know those will behave correctly as I've used both in the past.