Nov 20, 2008 #1 A ashishnetam Newbie level 2 Joined Nov 18, 2008 Messages 2 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,298 verilog assign Hi All, Can I use assign statement in verilog according to any active variable? For example suppose I want to use assign statement if active( any reg ) is enable (say high active). assign xyz = abc if (active ) other wise dont execute this statement at all. Is it possible to do in verilog? Thanks in advance Ashish
verilog assign Hi All, Can I use assign statement in verilog according to any active variable? For example suppose I want to use assign statement if active( any reg ) is enable (say high active). assign xyz = abc if (active ) other wise dont execute this statement at all. Is it possible to do in verilog? Thanks in advance Ashish
Nov 20, 2008 #2 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,409 Helped 14,749 Reputation 29,780 Reaction score 14,095 Trophy points 1,393 Location Bochum, Germany Activity points 298,048 verilog conditional assign I think the clearest way is to use an if statement in a combinational always block. It infers an asynchronous latch. Code: always @(active, abc) begin if (active) xyz <= abc; end The specification of all input signals is needed for correct simulation behaviour. The below statement should work, too: Code: assign xyz = (active)?abc:xyz;
verilog conditional assign I think the clearest way is to use an if statement in a combinational always block. It infers an asynchronous latch. Code: always @(active, abc) begin if (active) xyz <= abc; end The specification of all input signals is needed for correct simulation behaviour. The below statement should work, too: Code: assign xyz = (active)?abc:xyz;