Verilog combinational logic implementation, assign or always?

[u931803]

Verilog combinational logic coding style, assign or always?

Hello guys,

Today I had a discussion about Verilog coding style with a senior engineer

I personal prefer write combinational logic using assign
For example, assign cnt_w = incr ? cnt_r + 1 : cnt_r;

However, he said combinational logic should be coded using always for the following reason
1. Continuous assignment slows down simulation speed
2. Synthesis tool can optimize always better than assign
3. All assign can be realized by always, but not all always can be realized by assign

I agree with the first reason
But I wonder if the second is true with contemporary synthesis tools such as design compiler
Also I think assign and always are convertible both ways (except, of course, if you use for loop)

Does anyone have and idea?

Thanks a lot

 

[dave_59]

As a general statement, I don't believe any of those statements are correct.

1. For the same algorithm, code written in the highest level of abstraction will simulate the fastest. This might be at the expense of accurately modeling the propagation of physical delays or X's.
2. Again, the level of abstraction determines the level of difficulty for a synthesis tool to optimize your code. If you were to write the same code above as an always block, a synthesis tool would see it as equivalent.

   always @(incr or cnt_r) if (incr) 
                                            cnt_w = cnt_r + 1;
                                     else
                                     cnt_w =  cnt_r;

3. It is certainly easier to write some code with an always block using procedural code, but not impossible.

 

[u931803]

As a general statement, I don't believe any of those statements are correct.

1. For the same algorithm, code written in the highest level of abstraction will simulate the fastest. This might be at the expense of accurately modeling the propagation of physical delays or X's.
2. Again, the level of abstraction determines the level of difficulty for a synthesis tool to optimize your code. If you were to write the same code above as an always block, a synthesis tool would see it as equivalent.

   always @(incr or cnt_r) if (incr) 
                                            cnt_w = cnt_r + 1;
                                     else
                                     cnt_w =  cnt_r;

3. It is certainly easier to write some code with an always block using procedural code, but not impossible.

Thanks for you reply

That's what I thought, they should be the same as long as the intended underlying circuits are the same
He said that he attended a training course and the tutor with decent knowledge in synthesis tool pointed out synthesis tool tends to optimize always better than assign
But it was years ago, I am just wondering if this statement is still true or if it's actually never true

 

[rca]

Our design rule is to write the code in the clearest way, which means both are accepted, if that make the code simplest and readable.
I means a assign with multiple and or xor, could be not clear instead a if (a=xxxx &....).
During the code review, this could requested to change the code and a LEC tool will confirm the no functional modification.