Verilog coding for smaller mux?

[steven852]

Hi,

I have a mux coded in this way:

always @(*) begin
if (enable) begin
case(select)
4'b0000: ...
4'b0001: ...
4'b0010: ...
....
4'b1000: ...
endcase
end
end

Notice that the "select" only has full case for the lower 3 bits while the MSB is used only for one case. I tried to come up another mux with 3 control bits. Or something like this:

case({select[2],select[1],select[0]})
3'b000: ...
...
3'b111: ...
endcase

But what is the best coding style to handle the case when select[3]==1? Basically is it possible to avoid another mux to make the netlist simpler?

I think this solution will lower the area.

Thanks.

 

[ravurig]

I think u should check the relation between the case 4'b1000 with
other cases ,if some relation exists then u can implement only
2:0 mux.

Lets say 4'b1000: x = ~y;
4'b0000: x= y;
In the above case u don't require to write explictly 4'b1000.
use 2:0 mux and when [3] is 1 take output as finaly output = ~x;

hope I made it crystal clear.

 

[steven852]

I think my code has already implied a latch and a mux.

 

[wangkl]

if (enable)
begin
if (select[3]) // or (~ select[3])
begin
case (select[2:0])
...
...
endcase
end
else // select[3]
begin
end
end
else //enable
begin
end

 

[aravind]

u must specify full case or parallel.
otherwise it will infer latch .
other use complete case statement with default