Verilog Coding for Coin Acceptor

[Husaini]

Hello..so I have some project that I need to complete asap. So, can you guys help me about Verilog coding of coin acceptor?So, the coin acceptor can read the coin inserted and then display its value at FPGA 7-segment?

So this is the example video of what I want but this gentleman use VHDL but I want it in Verilog. Hope you guys can help me.

 

[barry]

First of all, I don’t think anybody is going to watch a 13 minute video; i’m not.

What, exactly, do you want? Do you want somebody to just write some Verilog for you so that you can ‘complete your project asap’? Plenty of people would do that for you, that’s how we make our living. What’s your budget?

 

[Husaini]

First of all, I don’t think anybody is going to watch a 13 minute video; i’m not.

What, exactly, do you want? Do you want somebody to just write some Verilog for you so that you can ‘complete your project asap’? Plenty of people would do that for you, that’s how we make our living. What’s your budget?

The time stamp is around 8:50. That is how I want my value stated at FPGA.

I want some help to complete my coding because of some error, not asking for “somebody to just write some Verilog” to complete it all. Yeah, I already ask many people and they said 300$ is still not enough. Satisfied?

 

[KlausST]

Hi,

I didn´t see this video --> I´m with Barry on this.
I´m used to schematics, flow charts, state diagrams...

Just focussing on the display:
since none of us knows what display this is, whether there is a display controller or not. If not: whther it is CC, CA, needs to be multiplexed..

I recommend you to go step by step:
* find out how it works
* write code for just enabling a single segment
* then write a decoder for displaying "0" to "9" on a single digit
* then write code for all digits. Multiplexed ot not..

Klaus

 

[dpaul]

@Husaini
I want some help to complete my coding because of some error, not asking for “somebody to just write some Verilog” to complete it all.
Then show us what you have done and where is the error?

This is a typical graduate school project and is not difficult (assuming that the task has been clearly described to you and understood by you).
Have you prepared a state-machine? if yes show us the state diagram.
If you have written some RTL, where is it?