# Verilog codes for clock divider

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#### kaiser

##### Newbie level 5 I have a 50 Mhz clock on my board and i need a 60Hz clock for my design......
Somebody can suggest anything to do...?
A verilog descripiton it will be very nice....(with comments- general mods)

#### nand_gates verilog code to measure the clk frequency

Here goes the Verilog code!

Code:
module clk_div(clk_50mhz, rst_n, clk_60hz);
input clk_50mhz, rst_n;
output      clk_60hz;
reg         clk_60hz;

reg [47:0]  counter;

always @(posedge clk_50mhz or negedge rst_n) begin
if (!rst_n) begin
counter <= 48'h00000;
clk_60hz <= 1'b0;
end else begin
if (counter == 48'h65B9A) begin
counter <= 48'h00000;
clk_60hz <= ~clk_60hz;
end else begin
counter <= counter + 1'b1;
end
end // else: !if(!rst_n)
end // always @ (posedge clk_50mhz or negedge rst_n)
endmodule // clk_div

### kaiser

Points: 2

#### sp

##### Full Member level 6 Re: CLK Divider HELP

i get it from one university... dunno its name D...

VHDL

Code:
If you need a slower clock, here is a simple clock divider algorithm, that divides the clock by 2N.

Where :

N = f(clk) / (2* f(desired))

-- file "clk_div.vhd"

-- a generic clock divider, divides by 2*N

------------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity clk_div is
generic(N: positive:= 2);
port
(fast_clk, reset: in std_logic;
slow_clk: buffer std_logic
);
end clk_div;

architecture behavioural of clk_div is
begin
process(reset, fast_clk)
variable count: natural;
begin
if reset = '1' then
count := 0;
slow_clk <= '0';
elsif rising_edge(fast_clk) then
count := count + 1;
if count = N then
slow_clk <= not slow_clk;
count := 0;
end if;
end if;
end process;
end behavioural;

regards,
sp

### kaiser

Points: 2

#### angelote Re: CLK Divider HELP

always @(posedge clk_50mhz or negedge rst_n) begin
if (!rst_n) begin

You will need dual edge filp-flop. Is your CPLD/FPGA capable?[/u]

### kaiser

Points: 2

##### Member level 5 Re: CLK Divider HELP

always @(posedge clk_50mhz or negedge rst_n) begin
if (!rst_n) begin

You will need dual edge filp-flop. Is your CPLD/FPGA capable?

There is no need to use dual edge flip-flop. That part of the verilog code is as writing in VHDL the following:
Code:
process(clk_50mhz, rst_n)
begin
if reset = '0' then
........
elsif rising_edge(clk_50mhz) then
.......

### kaiser

Points: 2

#### kaiser

##### Newbie level 5 Re: CLK Divider HELP

Thank you very much....

After i was looking over your suggestions, i made this(from 50Mhz downto 1Hz with 50% dutty cycle)

module clk_div ( clk_in, reset,clk_1hz);
input clk_in, reset;
output clk_1hz;
reg clk_1hz;

reg  counter;

always @(posedge clk_in or posedge reset)
begin
if (reset)
begin
counter <= 26'h0;
clk_1hz <= 1'b0;
end
else
begin
if (counter == 26'h17D7840)
begin
counter <= 26'h0;
clk_1hz <= ~clk_1hz;
end
else
counter <= counter + 1'b1;
end
end

endmodule

any comments it will be appreciated...

nand_gates said:
Here goes the Verilog code!

Code:
module clk_div(clk_50mhz, rst_n, clk_60hz);
input clk_50mhz, rst_n;
output      clk_60hz;
reg         clk_60hz;

reg [47:0]  counter;

always @(posedge clk_50mhz or negedge rst_n) begin
if (!rst_n) begin
counter <= 48'h00000;
clk_60hz <= 1'b0;
end else begin
if (counter == 48'h65B9A) begin
counter <= 48'h00000;
clk_60hz <= ~clk_60hz;
end else begin
counter <= counter + 1'b1;
end
end // else: !if(!rst_n)
end // always @ (posedge clk_50mhz or negedge rst_n)
endmodule // clk_div

But i dont understand something.......when i divide from 50 Mhz downto 60 hz ..well...i need "800.000 cycle of 50 MHz clock" /2= 400.000
and 400.000 = 48'h61A80 and in your code it a little bigger..so is not exactly 60Hz...right?
Why do you do that...? It's a trick and i dont know about it?

#### echo47 CLK Divider HELP

50 MHz does not divide evenly to 60 Hz. The ratio is 833333.333...

You could build a counter that counts up from 0 through 2499999 and outputs a pulse as it passes 0, 833333, and 1666666. That will give you three pulses every 2500000 clocks which is exactly 60 Hz. But the pulses are not evenly spaced, there is one-cycle jitter (20 ns).
Code:
module top (clk, hz60);
input             clk;
reg        [21:0] count = 0;
output reg        hz60 = 0;

always @ (posedge clk) begin
count <= (count == 2499999) ? 0 : count + 1;
hz60 <= (count == 0) | (count == 833333) | (count == 1666666);
end
endmodule
If you can't tolerate the 20 ns jitter, then you need to use a DLL or PLL to change the 50 MHz into something that can be divided cleanly.

#### omara007 Re: CLK Divider HELP

echo47 said:
That will give you three pulses every 2500000 clocks which is exactly 60 Hz. But the pulses are not evenly spaced, there is one-cycle jitter (20 ns).

How will it exactly be 60 Hz ? ..

don't you measure the frequency on ONE cycle basis ? .. can you tell me the duty cycle ?

#### echo47 CLK Divider HELP

My counter has 20ns period jitter. The period is 16666660ns, 16666660ns, 16666680ns, and then it repeats. The average of those three periods is 16666666.6666... nanoseconds, which is exactly 60 Hz.

Even the best clock oscillators have some jitter (usually picoseconds) due to thermal noise. You should always measure a clock's frequency by averaging many cycles.

#### mountain

##### Member level 2 Re: CLK Divider HELP

nand_gates said:
Here goes the Verilog code!

Code:
module clk_div(clk_50mhz, rst_n, clk_60hz);
input clk_50mhz, rst_n;
output      clk_60hz;
reg         clk_60hz;

reg [47:0]  counter;

always @(posedge clk_50mhz or negedge rst_n) begin
if (!rst_n) begin
counter <= 48'h00000;
clk_60hz <= 1'b0;
end else begin
if (counter == 48'h65B9A) begin
counter <= 48'h00000;
clk_60hz <= ~clk_60hz;
end else begin
counter <= counter + 1'b1;
end
end // else: !if(!rst_n)
end // always @ (posedge clk_50mhz or negedge rst_n)
endmodule // clk_div

1.
In the port definition, thers is
output clk_60hz;
reg clk_60hz;
why the "reg clk_60hz;" is needed? I met this type many times, but I don't know the reason.

2.
The counter is so long(48bit), so it will work well?

#### echo47 CLK Divider HELP

mountain,

1. Without the reg statement, the output signal would default to a wire instead of a register.
You can combine the two statements: output reg clk_60hz;

2. No, 48 bits is overkill. The upper 29 bits are always zero.

By the way, this module does not generate 60 Hz. It generates approximately 59.999952 Hz.

#### blueskystone

##### Newbie level 4 CLK Divider HELP

always @(posedge clk_50mhz or negedge rst_n) begin
if (!rst_n) begin

this design is ok , it is just an asynchronous RESET
, not a dual edge filp-flop.
it's suit for CPLD/FPGA .

#### kumar_eee Re: CLK Divider HELP

Can any1 explain abt Clock Doubler & How to implement it?....

#### echo47 Re: CLK Divider HELP

kumar_eee said:
Can any1 explain abt Clock Doubler & How to implement it?....
Implement it in what type of chip?
Modern FPGAs have built-in frequency synthesizers, such as the DCM in Xilinx devices. These can be used to multiply/divide the input clock frequency by various ratios.

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