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verilog code of a pipelined adder

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kumar_eee

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Pipeline implementation

How to implement a pipeline architecture using verilog coding?...
 

moneychaser

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Pipeline implementation

Take your combinational logic, and insert banks of registers between it.
 

bibo1978

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Re: Pipeline implementation

I hope it was this simple but it is not that simple, anyhow at the very simple level of pipelining you will have to duplicate the logic sometimes, other systems you must do a systolic design for it to save the latency and space .. not a simple task but you can start by the moneychaser idea.
 

deepa

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Re: Pipeline implementation

you can add dff's in each stage n synchronise them all at rising edges of the clk..in this manner your data will travel thro' each stage.
 

Hero

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Re: Pipeline implementation

I think that problem is not so easy.

For n-level pipeline system in the case of conditional jump you need to flush pipline queue, provide delay with (n-1) additional cycles and load pipeline queue n instructions on the jumped location.

In the case that you want to add BTC (Branch Traget Cache) unit to eliminate additional (n-1) execution cycles after every conditional jumps, you need to describe additional BTC unit and other interface logic with pipeline stages.

In some case pipeline stages are time and result dependant so you need to model all those complex relations.

Pipline stages are very complicated for exact software modeling and simultion. Some simulators use very simplified execution model to accelerate simulation process.

If you want to exactly model pipeline stages you can expect lot of hard work.
 

leonlin

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Re: Pipeline implementation

you can add dff's in each stage n synchronise them all at rising edges of the clk..in this manner your data will travel thro' each stage
 

kaustubhkhole

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Pipeline implementation

Can any one suggest any book for this implementation
 

mrnoone

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Pipeline implementation


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`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    14:31:04 09/28/06
// Design Name:    
// Module Name:    SLT16
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module SLT(y,x0,x1);
 
input [7:0] x0,x1;
output reg[7:0] y;
 
always @(x0 or x1)
begin
if(x1<x0)
y= 8'b1;
else
y=8'b0;
end  
 
 
endmodule
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    23:02:45 10/02/06
// Design Name:    
// Module Name:    Register
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module Register(out,in,load,clock,reset);
 
output reg[7:0] out;
input [7:0] in;
input load,clock,reset;
 
always @(posedge clock or posedge reset)
if(reset)
out=8'b0000_0001;
else
if(load)
out=in;
 
endmodule
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    23:12:34 10/02/06
// Design Name:    
// Module Name:    PC
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module ProgCounter(out,clock,reset);
 
output reg [7:0] out;
input clock,reset;
 
always @(posedge reset or posedge clock)
if(reset)
out<=8'b0000_0000;
else
out<=out+1;
 
 
 
endmodule
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    23:12:34 10/02/06
// Design Name:    
// Module Name:    PC
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module ProgCounter(out,clock,reset);
 
output reg [7:0] out;
input clock,reset;
 
always @(posedge reset or posedge clock)
if(reset)
out<=8'b0000_0000;
else
out<=out+1;
 
 
 
endmodule
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    23:12:34 10/02/06
// Design Name:    
// Module Name:    PC
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module ProgCounter(out,clock,reset);
 
output reg [7:0] out;
input clock,reset;
 
always @(posedge reset or posedge clock)
if(reset)
out<=8'b0000_0000;
else
out<=out+1;
 
 
 
endmodule
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    23:12:34 10/02/06
// Design Name:    
// Module Name:    PC
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module ProgCounter(out,clock,reset);
 
output reg [7:0] out;
input clock,reset;
 
always @(posedge reset or posedge clock)
if(reset)
out<=8'b0000_0000;
else
out<=out+1;
 
 
 
endmodule


next time i will give all the code
 

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