Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

verilog code of a pipelined adder

Status
Not open for further replies.

kumar_eee

Advanced Member level 3
Joined
Sep 22, 2004
Messages
814
Helped
139
Reputation
276
Reaction score
109
Trophy points
1,323
Location
Bangalore,India
Activity points
4,676
Pipeline implementation

How to implement a pipeline architecture using verilog coding?...
 

moneychaser

Junior Member level 2
Joined
Aug 28, 2004
Messages
20
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
180
Pipeline implementation

Take your combinational logic, and insert banks of registers between it.
 

bibo1978

Full Member level 4
Joined
May 1, 2004
Messages
210
Helped
12
Reputation
24
Reaction score
6
Trophy points
1,298
Activity points
2,548
Re: Pipeline implementation

I hope it was this simple but it is not that simple, anyhow at the very simple level of pipelining you will have to duplicate the logic sometimes, other systems you must do a systolic design for it to save the latency and space .. not a simple task but you can start by the moneychaser idea.
 

deepa

Full Member level 2
Joined
Jul 3, 2005
Messages
127
Helped
3
Reputation
6
Reaction score
2
Trophy points
1,298
Activity points
2,226
Re: Pipeline implementation

you can add dff's in each stage n synchronise them all at rising edges of the clk..in this manner your data will travel thro' each stage.
 

Hero

Full Member level 2
Joined
Mar 6, 2002
Messages
145
Helped
4
Reputation
8
Reaction score
2
Trophy points
1,298
Activity points
1,608
Re: Pipeline implementation

I think that problem is not so easy.

For n-level pipeline system in the case of conditional jump you need to flush pipline queue, provide delay with (n-1) additional cycles and load pipeline queue n instructions on the jumped location.

In the case that you want to add BTC (Branch Traget Cache) unit to eliminate additional (n-1) execution cycles after every conditional jumps, you need to describe additional BTC unit and other interface logic with pipeline stages.

In some case pipeline stages are time and result dependant so you need to model all those complex relations.

Pipline stages are very complicated for exact software modeling and simultion. Some simulators use very simplified execution model to accelerate simulation process.

If you want to exactly model pipeline stages you can expect lot of hard work.
 

leonlin

Newbie level 4
Joined
Nov 9, 2004
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
118
Re: Pipeline implementation

you can add dff's in each stage n synchronise them all at rising edges of the clk..in this manner your data will travel thro' each stage
 

kaustubhkhole

Member level 3
Joined
Jan 21, 2006
Messages
58
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,288
Activity points
1,674
Pipeline implementation

Can any one suggest any book for this implementation
 

mrnoone

Newbie level 4
Joined
Sep 18, 2006
Messages
7
Helped
2
Reputation
4
Reaction score
1
Trophy points
1,283
Activity points
1,787
Pipeline implementation


Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    14:31:04 09/28/06
// Design Name:    
// Module Name:    SLT16
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module SLT(y,x0,x1);
 
input [7:0] x0,x1;
output reg[7:0] y;
 
always @(x0 or x1)
begin
if(x1<x0)
y= 8'b1;
else
y=8'b0;
end  
 
 
endmodule
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    23:02:45 10/02/06
// Design Name:    
// Module Name:    Register
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module Register(out,in,load,clock,reset);
 
output reg[7:0] out;
input [7:0] in;
input load,clock,reset;
 
always @(posedge clock or posedge reset)
if(reset)
out=8'b0000_0001;
else
if(load)
out=in;
 
endmodule
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    23:12:34 10/02/06
// Design Name:    
// Module Name:    PC
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module ProgCounter(out,clock,reset);
 
output reg [7:0] out;
input clock,reset;
 
always @(posedge reset or posedge clock)
if(reset)
out<=8'b0000_0000;
else
out<=out+1;
 
 
 
endmodule
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    23:12:34 10/02/06
// Design Name:    
// Module Name:    PC
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module ProgCounter(out,clock,reset);
 
output reg [7:0] out;
input clock,reset;
 
always @(posedge reset or posedge clock)
if(reset)
out<=8'b0000_0000;
else
out<=out+1;
 
 
 
endmodule
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    23:12:34 10/02/06
// Design Name:    
// Module Name:    PC
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module ProgCounter(out,clock,reset);
 
output reg [7:0] out;
input clock,reset;
 
always @(posedge reset or posedge clock)
if(reset)
out<=8'b0000_0000;
else
out<=out+1;
 
 
 
endmodule
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    23:12:34 10/02/06
// Design Name:    
// Module Name:    PC
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module ProgCounter(out,clock,reset);
 
output reg [7:0] out;
input clock,reset;
 
always @(posedge reset or posedge clock)
if(reset)
out<=8'b0000_0000;
else
out<=out+1;
 
 
 
endmodule


next time i will give all the code
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top