Verilog code gets compiled but does not simulate

[Hacralo]

I have typed a verilog code for a simple half adder block using cadence.
I have compiled the program and it does not show any errors.
when i used the tcl script.
"irun -clean *.v -input probe.tcl -access +rwc -timescale 1ns/1ns &"
the files get compiled and simulate too.
when when i run the test bench using command
"irun -clean {test_bench_name}.v -input probe.tcl -access +rwc -timescale 1ns/1ns &"
it gives the following error
|
ncelab: *E,CUVMUR (./ha_t.v,4|5): instance 'ha_tb.gut' of design unit 'ha' is unresolved in 'worklib.ha_tb:v'.
irun: *E,ELBERR: Error during elaboration (status 1), exiting.
my module and testbench are attached

 

[sharath666]

You need to define the "and" and "xor" functions used in module ha.

 

[harpv]

In your first command you have compiled both the design and the testbench (*.v) but in the second command you have compiled only your testbench. So when the simulator tries to elaborate your testbench its unable to find the design (ha).

Albeit, if you run the second command after running the first command without the -clean option, I guess you might still be able to run the simulation. You can give it a try.

>> irun -clean *.v -input probe.tcl -access +rwc -timescale 1ns/1ns &
>> irun {test_bench_name}.v -input probe.tcl -access +rwc -timescale 1ns/1ns &

 

[ads-ee]

You need to define the "and" and "xor" functions used in module ha.

You don't know Verilog then. XOR and AND are keywords in the language.

In your first command you have compiled both the design and the testbench (*.v) but in the second command you have compiled only your testbench. So when the simulator tries to elaborate your testbench its unable to find the design (ha).

Another option is to add `include ha.v in your testbench file.