Verilog code for a cascadable 4 to 2 priority encoder

[farhanashirin]

Hi,

I faced some these following problems,anybody can help me?

1.Write a verilog description for the following function.
f(A,B,C,D)=Σm(0,2,4,5,6,7,9,10,11), d(1,13)

2.Show verilog code for a cascadable 4 to 2 priority encoder.Your circuit should have an enable input,four data inputs,an enable output,an interrupt output,and two source id outputs.All input and outputs must be active high.for cascading purposes and to be able to use wired -OR logic,use tri-state for ur id outputs.Adjust the details of your design for a better cascading capability.

thanks in advance.\][/url][/code]

 

[nand_gates]

Re: Please help me

Here goes the solutions.. Hope this helps!

1.

module func (
   // Outputs
   Y, 
   // Inputs
   A, B, C, D
   );
   input A,B,C,D;
   output [3:0] Y;
   reg [3:0] Y;
   always @(A or B or C or D)
     case ({A,B,C,D})
       0,2,4,5,6,7,9,10,11 : Y = 1;
       default : Y = 13;
     endcase // case({A,B,C,D})
endmodule // func

2.

/*
+------------+-------------+
| Inputs     |   Outputs   |
+--+---------+-------------+
|EI| 0 1 2 3 | A1 A0 GS EO |
+--+---------+-------------+
|0 | X X X X | 0  0  0  0  |
|1 | 0 0 0 0 | 0  0  0  1  |
|1 | X X X 1 | 1  1  1  0  |
|1 | X X 1 0 | 1  0  1  0  |
|1 | X 1 0 0 | 0  1  1  0  |
|1 | 1 0 0 0 | 0  0  1  0  |
+------------+-------------+
*/
module pri_enc (
   // Outputs
   id, e0, int, 
   // Inputs
   i0, i1, i2, i3, ei
   );
   input i0,i1,i2,i3;
   input ei;
   output [1:0] id;
   output       e0, int;
   reg [1:0] id;
   reg       e0;
   assign    int = ei & ~e0;
   
   always @(ei or i0 or i1 or i2 or i3) begin
      id = 0;
      e0 = 0;
      casex ({ei,i0,i1,12,i3})
        5'b10000 : e0 = 1;
        5'b1xxx1 : id = 0;
        5'b1xx10 : id = 1;
        5'b1x100 : id = 2;
        5'b11000 : id = 3;
      endcase
   end
endmodule // pri_enc

In second soln. note that id outputs are not tri state as per
requirement.