sagar m hegde
Newbie level 1
HI ALL,
we worked on the verilog code and managed to write a code (which i have attached)..
But did not yield the required result.. plz help
Also we are interested in verilog code for syndrome calculation which detects the error and shows in which bit error have happened..
plz assist us
we r writing something what we have done in the code
code (24,8)
data 8 bit , 16 bit crc , net 24 bit
eg:-data=11111111 G(x)=x^16+x^12+x^5+1
expected crc=R(x)=x^12+x^11+x^10+x^9+x^7+x^6+x^5+x^4
ie R=0001111011110000
CODE 16
module crc16_parallel(
input [7:0] data_in,
output reg[15:0] crc16,
input rst,
input clk);
// LFSR for USB CRC16
function [15:0] crc16_serial;
input [15:0] crc;
input data;
begin
crc16_serial[0] = crc[15] ^ data;
crc16_serial[1] = crc[0];
crc16_serial[2] = crc[1];
crc16_serial[3] = crc[2];
crc16_serial[4] = crc[3];
crc16_serial[5] = crc[4]^crc[15] ^ data;
crc16_serial[6] = crc[5];
crc16_serial[7] = crc[6];
crc16_serial[8] = crc[7];
crc16_serial[9] = crc[8];
crc16_serial[10] = crc[9]
crc16_serial[11] = crc[10];
crc16_serial[12] = crc[11] ^ crc[15] ^ data;
crc16_serial[13] = crc[12];
crc16_serial[14] = crc[13];
crc16_serial[15] = crc[14];
end
endfunction
// 8 iterations of USB CRC5 LFSR
function [15:0] crc_iteration;
input [15:0] crc;
input [7:0] data;
integer i;
begin
crc_iteration = crc;
for(i=0; i<8; i=i+1)
crc_iteration = crc16_serial(crc_iteration, data);
end
endfunction
always @(posedge clk, posedge rst) begin
I f(rst) begin
crc16 <= 16'h1F;
end
else begin
crc16 <= crc_iteration(crc16,data_in);
end
end
endmodule
we worked on the verilog code and managed to write a code (which i have attached)..
But did not yield the required result.. plz help
Also we are interested in verilog code for syndrome calculation which detects the error and shows in which bit error have happened..
plz assist us
we r writing something what we have done in the code
code (24,8)
data 8 bit , 16 bit crc , net 24 bit
eg:-data=11111111 G(x)=x^16+x^12+x^5+1
expected crc=R(x)=x^12+x^11+x^10+x^9+x^7+x^6+x^5+x^4
ie R=0001111011110000
CODE 16
module crc16_parallel(
input [7:0] data_in,
output reg[15:0] crc16,
input rst,
input clk);
// LFSR for USB CRC16
function [15:0] crc16_serial;
input [15:0] crc;
input data;
begin
crc16_serial[0] = crc[15] ^ data;
crc16_serial[1] = crc[0];
crc16_serial[2] = crc[1];
crc16_serial[3] = crc[2];
crc16_serial[4] = crc[3];
crc16_serial[5] = crc[4]^crc[15] ^ data;
crc16_serial[6] = crc[5];
crc16_serial[7] = crc[6];
crc16_serial[8] = crc[7];
crc16_serial[9] = crc[8];
crc16_serial[10] = crc[9]
crc16_serial[11] = crc[10];
crc16_serial[12] = crc[11] ^ crc[15] ^ data;
crc16_serial[13] = crc[12];
crc16_serial[14] = crc[13];
crc16_serial[15] = crc[14];
end
endfunction
// 8 iterations of USB CRC5 LFSR
function [15:0] crc_iteration;
input [15:0] crc;
input [7:0] data;
integer i;
begin
crc_iteration = crc;
for(i=0; i<8; i=i+1)
crc_iteration = crc16_serial(crc_iteration, data);
end
endfunction
always @(posedge clk, posedge rst) begin
I f(rst) begin
crc16 <= 16'h1F;
end
else begin
crc16 <= crc_iteration(crc16,data_in);
end
end
endmodule