Verilog code doubts about using posedge pulse and posedge clk

[no_mad]

verilog code doubts

Hi all,

Here is the problem.

A)

always @(posedge pulse or posedge rst)
begin
	if(rst)
		active_H <= 0;
	else 
		active_H <= 1;
end

B)
always @(posedge clk or posedge rst)
begin
	if(rst)
		active_H <= 0;
	else if(pulse)
		active_H <= 1;
	else
		active_H <= active_H;
end
[\code]
# The size of pulse signal is 1 clock cycle of clk. (posedge to posedge)

Questions:
1)	Which one is better? What is the impact to my design? (timing, synthesis)
2)	Instead of using posedge clk to capture pulse signal, is it a good practice to use negedge clk? I have seen some people prefer to use negedge clk to capture pulse signal. The reason is pulse signal already stable. Thus, no timing violation. That's what these people told me.  

In my opinion,
1)	I think (B) is better than (A) because it would be much easier to synthesis and perform STA. I need to constraint only one clock, clk. Otherwise; I need to constraint pulse signal as a clock signal. 
2)	I would prefer to use posedge clk rather than negedge clk to capture the pulse signal. Any issue will deal later during synthesis. Tweak the design or tighter the timing constraint.

Please give your opinion and feedback to my 2 cents opinion.
Highly appreciate. Thanks
:?:

 

[vicky3661]

Re: verilog code doubts

hi
if you are using pulse as your input then according to me method B is better than A. else method A is good. if u r using pulse as yur input, then method A will infer a latch. so go with method B.

 

[asicganesh]

verilog code doubts

Method B is better because if Method A is used then u need to also add pulse as clock constraint to avoid inferring a latch..

 

[gentle_man]

verilog code doubts

Method A is async design while Method B is a sync design.

Most tools support sync design better now

 

[no_mad]

verilog code doubts

Thanks for reply.

However, what do u guys think about the second question? Any comment on that.

Thanks in advance.