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verilog code confusion

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yann_sun

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Hi, all
My question is why neg_A and neg_B are unequal.
To be specific, neg_A derives from the last negative edge of A, however, neg_B is the present negative edge of B.

Stimulus A and B are the same.



Here is the code

always @(A) begin
if(A) pos_A=$realtime;
else neg_A=$realtime;
end

always @(negedge B) begin
neg_B=$realtime;
$display("%f",neg_A);
$display("%f",neg_B);
end
 

I think the reson is that the always blocks execution sequence is not defined by IEEE standart, so simulator can evaluate first always @(A) block and after always @(negedge B) or vice-versa.
If always @(negedge B) will be evaluated first you will see the new value for neg_B and the old one (from the previous neg A event) for neg_A...

Read more about event shedule during the simulation process here.
 
Last edited:

Thanks Alosevskoy,
What do you mean by if?
Is it evaluated randomly?
Does it depend on different simulator?

---------- Post added at 02:50 ---------- Previous post was at 02:49 ----------

Thanks Alosevskoy,
What do you mean by if?
Is it evaluated randomly?
Does it depend on different simulator?
 

Yes, as I understand different simulator may create different event sequences in which always blocks are evaluated, so the results are different )

What the simulator do you use? I tried to model following code and neg_A and neg_B were the same (simulator ISim from Xilinx ISE)...

Code:
module tb(
    );

realtime pos_A, neg_A, neg_B;

reg tgl_Ev = 0;

always #(10) tgl_Ev = ~tgl_Ev;

always @(tgl_Ev) begin
   if(tgl_Ev) pos_A=$realtime;
   else neg_A=$realtime;
end

always @(negedge tgl_Ev) begin
   neg_B=$realtime;
   
   $display("----------------------");
   $display("%f",neg_A);
   $display("%f",neg_B);
end

initial
   #(100) $finish;

endmodule
 

I've just tried to model this code with free Icarus Verilog (iverilog) simulator and it gave me a different result:
----------------------
0.000000
20.000000
----------------------
20.000000
40.000000
----------------------
40.000000
60.000000
----------------------
60.000000
80.000000

The results from ISim and ModelSim are the same:
----------------------
20.000000
20.000000
----------------------
40.000000
40.000000
----------------------
60.000000
60.000000
----------------------
80.000000
80.000000
 

I'm using vcs.
Vcs got the same result as iverilog by simulating your tb code.
 

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