Verilog Code: assign c = (a == b)

[AutoDriver]

What does it mean?

 

[FvM]

The result of the compare operation a==b is assigned to c.

 

[trav1s]

I've never used this syntax before, but if it is compilable, it must mean c is the exclusive nor of a and b. It is using the equality operator to check if a is the same logical level as b. I would write it using the Verilog XNOR operator, since it is more intuitive to me:
assign c = a ~^ b;

 

[FvM]

I would write it using the Verilog XNOR operator, since it is more intuitive to me

Consider, that a and b may be bit vectors as well. Then the result of XNOR and compare would be different.

 

[vishal0122]

If both the vectors are equal then result will be logic level '1' else '0'.

 

[trav1s]

Good point, I had made an assumption that a and b are each 1 bit, based on incomplete context. For the case where a and b are vectors of equal and arbitrary size you could get the desired behavior by ANDing all the bits from my previous equation as follows:
assign c = &(a ~^ b);
But that seems unnecessarily confusing.
I ran the original syntax (a == b) through Cadence's HAL lint checker, and theres no problem with it at all, so perhaps it is the most ideal solution.