Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Verilog Code: assign c = (a == b)

Status
Not open for further replies.

FvM

Super Moderator
Staff member
Joined
Jan 22, 2008
Messages
47,928
Helped
14,143
Reputation
28,545
Reaction score
12,827
Trophy points
1,393
Location
Bochum, Germany
Activity points
278,099
The result of the compare operation a==b is assigned to c.
 

trav1s

Advanced Member level 4
Joined
Nov 11, 2010
Messages
100
Helped
29
Reputation
60
Reaction score
28
Trophy points
1,318
Location
Japan
Activity points
2,025
I've never used this syntax before, but if it is compilable, it must mean c is the exclusive nor of a and b. It is using the equality operator to check if a is the same logical level as b. I would write it using the Verilog XNOR operator, since it is more intuitive to me:
assign c = a ~^ b;
 

FvM

Super Moderator
Staff member
Joined
Jan 22, 2008
Messages
47,928
Helped
14,143
Reputation
28,545
Reaction score
12,827
Trophy points
1,393
Location
Bochum, Germany
Activity points
278,099
I would write it using the Verilog XNOR operator, since it is more intuitive to me
Consider, that a and b may be bit vectors as well. Then the result of XNOR and compare would be different.
 

vishal0122

Newbie level 2
Joined
Nov 10, 2009
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Ahmedabad
Activity points
1,304
If both the vectors are equal then result will be logic level '1' else '0'.
 

trav1s

Advanced Member level 4
Joined
Nov 11, 2010
Messages
100
Helped
29
Reputation
60
Reaction score
28
Trophy points
1,318
Location
Japan
Activity points
2,025
Good point, I had made an assumption that a and b are each 1 bit, based on incomplete context. For the case where a and b are vectors of equal and arbitrary size you could get the desired behavior by ANDing all the bits from my previous equation as follows:
assign c = &(a ~^ b);
But that seems unnecessarily confusing.
I ran the original syntax (a == b) through Cadence's HAL lint checker, and theres no problem with it at all, so perhaps it is the most ideal solution.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top