[SOLVED] Verilog clock divider 50 MHz to 1 MHz

[hsnhsyn1]

hi, i'm new to the forum and FPGA.

i'm designing a simple clock divider from 50 MHz as parameterized for a small part of a project.
my code is successfully compiled but when i try to simulate it with quartus timing analyzer, the output clock is all X.
i suppose there's something wrong with the output assignment.
any help would be helpful.
and here is the verilog code and also simulation capture.

// Clock divider circuit
// From 50 MHz to 1 MHz/200 Hz with %50 duty cycle

module clk_div(Clk_in, Clk_out);

// input ports
input Clk_in;

// output ports
output reg Clk_out;

// counter size calculation according to input and output frequencies
parameter sys_clk = 50000000;	// 50 MHz system clock
parameter clk_out = 1000000;	// 1 MHz clock output
parameter max = sys_clk / (2*clk_out); // max-counter size

reg [4:0]counter = 0; // 5-bit counter size

always@(posedge Clk_in) begin
	if (counter == max-1)
		begin
		counter <= 0;
		Clk_out <= ~Clk_out;
		end
	else
		begin
		counter <= counter + 1'd1;
		end
	Clk_out <= (counter == 5'd0);
	end
endmodule

https://obrazki.elektroda.pl/4895845300_1363727509.png

 

[mrflibble]

Looks like you almost got it! You'll just have to change one line. Change to:

output reg Clk_out = 1'b0; // provide initial condition for this register.

That makes sure that your simulation engine knows what the register content is on t=0. In real hardware this is not so much of an issue since by default the flipflops will start out as 0. Unless of course your design dictates otherwise, hence the "by default".

And you may want to remove that "Clk_out <= (counter == 5'd0);" line, because you already do your clock toggle in the "if (counter == max-1)" part.

 

[hsnhsyn1]

okay, thanks for the answer and now i have another question. in the simulation report, when i look the output clock period it's 995,66 ns, the first half is 495,66 ns and the second half is 500 ns. what's causing this difference? because i got the same result when i design the divider with vhdl.

 

[mrflibble]

The difference is caused by observer error. ;-) You will note that both the rising edge AND the falling edge of your Clk_out signal are shifted in relation to your Clk_in signal. If you ignore the first transition (the one causing you to make the wrong assumption) and then look at the next few you'll see what I mean. Run the simulation for say 10000 ns, so you'll see a few more transitions.

 

[hsnhsyn1]

and another simple question about simulator: i've tried to run the simulation for 10000 ns as you suggested by selecting "end simulation at: " setting, but it still shows only one transition of the divided clock signal, for 1 us. any suggestion about that would be appreciated?

 

[mrflibble]

That doesn't sound right ... can you post the full code for both your current version of the clock divider module AND the testbench? Saves us a lot of assumptions.

 

[hsnhsyn1]

this is the current divider module. but i didn't use a testbench, i tried to use the simulator within the quartus 2. i don't know how to write a testbench yet so just used the simulator tool with a vector waveform file.

// Clock divider circuit
// From 50 MHz to 1 MHz/200 Hz with %50 duty cycle

module clk_div(Clk_in, Clk_out);

// input ports
input Clk_in;

// output ports
output reg Clk_out;

// counter size calculation according to input and output frequencies
parameter sys_clk = 50000000;	// 50 MHz system clock
parameter clk_out = 1000000;	// 1 MHz clock output
parameter max = sys_clk / (2*clk_out); // max-counter size

reg [4:0]counter = 0; // 5-bit counter size

always@(posedge Clk_in) begin
	if (counter == max-1)
		begin
		counter <= 0;
		Clk_out <= ~Clk_out;
		end
	else
		begin
		counter <= counter + 1'd1;
		end
	end
endmodule

 

[j_andr]

if you use quartus simulator there is on way to get 'X'
as you simulate netlist;
you can see 'X' in simulation only if you forget to add all input
signals to the waweform;

looks like you haven't set:
settings->simulator settings->simulator output files:
"overwrite simulation input file with simulation results"
so you see your inputs, not sim. results

j.

 

[hsnhsyn1]

and my simulations always stop at about 1 us. whether or not i specify the "end simulation at: " time, it always stops at the same value. so i can only see one transition for the divided clock cycle.

 

[hsnhsyn1]

by the way, thanks all for your help. i managed to see my design works well. i set the end time for the simulation by Edit > End time.