Verilog Challenges: always @*

[choonlle]

what is different between always @* and always @(*)?


always @(*)
begin

will use = blocking

always @*
... will use <= ( non blocking )

 

[bbgil]

hi,

Procedural assignment allows an alternative, often higher-level, behavioral
description of combinational logic. Two structured procedure statements: initial and always. Edge-triggered circuits are described using a sequential always block
Example:
module combinational(a, b, sel,
out);
input a, b;
input sel;
output out;
reg out;
always @ (a or b or sel)
begin
if (sel) out = a;
else out = b;
end
endmodule

Sequential always block example:
module sequential(a, b, sel,
clk, out);
input a, b;
input sel, clk;
output out;
reg out;
always @ (posedge clk)
begin
if (sel) out <= a;
else out <= b;
end
endmodule

The use of posedge and negedge makes an always block sequential
(edge-triggered). Unlike a combinational always block, the sensitivity list does
determine behavior for synthesis!

Blocking assignment: evaluation and assignment are immediate
example:
always @ (a or b or c)
begin
x = a | b;
y = a ^ b ^ c;
z = b & ~c;
end

Nonblocking assignment: all assignments deferred until all right-hand
sides have been evaluated (end of simulation timestep)
Example:
always @ (a or b or c)
begin
x <= a | b;
y <= a ^ b ^ c;
z <= b & ~c;
end
Sometimes, as above, both produce the same result. Sometimes, not!Blocking assignments do not reflect the intrinsic behavior of multi-stage sequential logic

Guideline: use nonblocking assignments for sequential always blocks

Hope this help.

 

[choonlle]

thanks for your reply


Then , should u explain what is different between always @* and always @(*)

 

[sree205]

Hi,
i don't have a great knowledge on the difference, but, i know that verilog-2001 suggests always@* which will make the signals on the RHS to be added to the sensitivity list. i think its got nothing to do with non-blocking statements.

i also know that (* ........ *) is used for other purpose. will check back and let u know on (*) .

in the mean time, if u would like to get more info, please refer clifford cumming's article on verilog 2001.