verilog basic question on aynsc reset ???

[mohi@608]

well i want to have a async reset which is active high on a block which is operating at posedge of sys clock..
my code is as follows.......

always@(posedge sys_clk or posedge reset)
begin
if(reset)
......
.,,,
end(

my doubt is can we use both sy_clk and reset at posedge in order to fullfill the async condition ???...or is there any other method ???

 

[dave_59]

There may be other methods, but this style is imposed by synthesis tools to generate the proper hardware logic.

The keyword posedge just means wait for the rising edge of a signal. And because you are waiting for two independent signal edges, they may be asynchronous to each other. If you had only

always @(posedge sys_clk)

Then the if (reset) would only be checked at the rising edge of sys_clk, making it synchronous.

 

[babaduredi]

since you have active high reset, most of the time it will be held low.What i suggest to use 2 separate always block.
always@(reset)
begin
...
end
always@(posedge sys_clk)
begin
if(~reset)
...
end

This would implement async reset as reset got nothing to do with clock. There will be time when system will see reset high at posedge of sys_clk, so implement second always block carefully.