Mar 14, 2016 #1 S shaiko Advanced Member level 5 Joined Aug 20, 2011 Messages 2,644 Helped 303 Reputation 608 Reaction score 297 Trophy points 1,363 Activity points 18,302 Hello, What does this code do? assign y= & x;
Mar 14, 2016 #2 K kvingle Full Member level 5 Joined Nov 5, 2007 Messages 244 Helped 33 Reputation 66 Reaction score 12 Trophy points 1,298 Location India. Activity points 2,574 '&' is doing a bitwise and operation. i.e. all bits of signal 'x' will be anded with each other and resultant value would be assigned to Y.
'&' is doing a bitwise and operation. i.e. all bits of signal 'x' will be anded with each other and resultant value would be assigned to Y.
Mar 14, 2016 #3 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,426 Helped 14,752 Reputation 29,786 Reaction score 14,103 Trophy points 1,393 Location Bochum, Germany Activity points 298,122 LRM 11.4.9 Reduction operators
Mar 14, 2016 #4 S shaiko Advanced Member level 5 Joined Aug 20, 2011 Messages 2,644 Helped 303 Reputation 608 Reaction score 297 Trophy points 1,363 Activity points 18,302 LRM 11.4.9 Reduction operators Click to expand... I knew what '&' What I wasn't familiar with is the single line statement.
LRM 11.4.9 Reduction operators Click to expand... I knew what '&' What I wasn't familiar with is the single line statement.
Mar 14, 2016 #5 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,426 Helped 14,752 Reputation 29,786 Reaction score 14,103 Trophy points 1,393 Location Bochum, Germany Activity points 298,122 Assignment operations are mostly single line, isn't it?
Mar 14, 2016 #6 S shaiko Advanced Member level 5 Joined Aug 20, 2011 Messages 2,644 Helped 303 Reputation 608 Reaction score 297 Trophy points 1,363 Activity points 18,302 Sorry, I meant "single argument" - not "single line". In VHDL unary operators weren't possible before 2008, I didn't know Verilog supports it.
Sorry, I meant "single argument" - not "single line". In VHDL unary operators weren't possible before 2008, I didn't know Verilog supports it.
Mar 14, 2016 #7 ads-ee Super Moderator Staff member Joined Sep 10, 2013 Messages 7,944 Helped 1,822 Reputation 3,654 Reaction score 1,808 Trophy points 1,393 Location USA Activity points 60,207 Verilog has always supported this unary reduction operator, even my book from '93 (pre-IEEE standardization '95) shows it. VHDL has been slowly copying stuff from Verilog over the years.
Verilog has always supported this unary reduction operator, even my book from '93 (pre-IEEE standardization '95) shows it. VHDL has been slowly copying stuff from Verilog over the years.