Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] verilog and vhdl in same project, problems

Status
Not open for further replies.

punj33

Newbie level 6
Joined
Jan 2, 2010
Messages
13
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,385
As a part of my project, I need to interface with DDR SDRAM and I have an IP core of RAM controller. However, my whole project is in Verilog and the ip i got is in VHDL.

So, can a project have both VHDL and Verilog ?

I saw in the forums and learnt about XHDL. How efficient is it? I tried to convert one of the files of the controller but the demo refused to convert citing the file is too large. Are there any free sources or any other alternatives ?
 

devas

Full Member level 2
Joined
Jun 16, 2009
Messages
129
Helped
42
Reputation
84
Reaction score
11
Trophy points
1,298
Activity points
2,004
Hi,

You can mix VHDL and Verilog if your simulator and synthesizer supports both languages (is sometimes an add-on feature).

In your Verilog code instantiate your VHDL ip-core just like if it was a Verilog module.

Devas
 
  • Like
Reactions: punj33

    punj33

    Points: 2
    Helpful Answer Positive Rating

punj33

Newbie level 6
Joined
Jan 2, 2010
Messages
13
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,385
thank you. I am using Xilinx 10.1 and i reckon it should support .
It means i dont need any thing like XHDL, isn't it. Thats a relief
 

devas

Full Member level 2
Joined
Jun 16, 2009
Messages
129
Helped
42
Reputation
84
Reaction score
11
Trophy points
1,298
Activity points
2,004
Hi,

When your simulator/synthesizer has mixed language support there is no need for XHDL.

Devas
 

punj33

Newbie level 6
Joined
Jan 2, 2010
Messages
13
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,385
I tried a simple program where I instantiated vhdl from my verilog code

library ieee;
use ieee.std_logic_1164.all;

entity mainvhdl_en is
port (in1,in2:in std_logic;
out1,out2:eek:ut std_logic);
end entity;

architecture mainvhdl_arch of mainvhdl_en is
begin
out1<=in1 or in2;
out2<=in1 and in2;
end architecture;

module test1(a,b,c,d);
input a,b;
output reg c,d;
mainvhdl_en mainvhdl_en1(.in1(a),.in2(b),.out1(c),.out2(d));
endmodule


Then the error I get in modelsim when i try to simulate the verilog module is :

# ** Fatal: (vsim-3364) Illegal Verilog connection (3rd) for VHDL output port 'out1'.
# Time: 0 ns Iteration: 0 Instance: /test1/mainvhdl_en1 File: vh.vhd Line: 6
# FATAL ERROR while loading design
# Error loading design

do I have to change some settings in modelsim like mixed language sth ?
 

FvM

Super Moderator
Staff member
Joined
Jan 22, 2008
Messages
49,129
Helped
14,380
Reputation
29,024
Reaction score
13,133
Trophy points
1,393
Location
Bochum, Germany
Activity points
283,194
When mixing VHDL and Verilog design entities, you have to keep the syntax rules of both languages.
Your example is using illegal Verilog syntax in the module instantiation, the problem hasn't to do with VHDL or Verilog module. You simply can't connect a variable of the reg type with a module output port. It has to be a wire.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top