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[SOLVED] verilog and system verilog for behavioral models

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DharmaSlice

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Hi,

I have a requirement to define an output with a more 'analog' feel then the straight forward digital definition that I currently have in place.

dac_out is defined as a digital output

This is simply 1 or 0 based on:

------

module DAC (IOUTN, IOUTP, VDDA1V8,, BIAS, CLK, DAC,
);

inout VDDA1V8;
input BIAS;
input CLK;
input [13:0] DAC;

output IOUTP, IOUTN;



assign IOUTP = (output_enable) ? (ioutp_sb > 16383) ? 1'b1 : 1'b0 : 1'bX;
assign IOUTN = (output_enable) ? (ioutn_sb < 18384) ? 1'b1 : 1'b0 : 1'bX;


------


IOUTP goes high if the signal ioutp_sb is above 16383


with the real (analog type signal) being defined as:


// channel 'real' DAC output
ioutp_real = (output_enable) ? ($itor(dac_in_1) / (2.0**15.0 - 2.0)) : 0.0;
ioutn_real = (output_enable) ? ((16383.0 - $itor(dac_in_1)) / (2.0**15.0 - 2.0)) : 0.0;



I simply want to map this real signal to my actual output (without breaking the fact that the output is a single wire and not a huge bus of signals)

Is this possible with system verilog ? How ?

Thanks
 

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