Verilog-ams vs Verilog-A

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ankitgarg0312

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please tell me difference in verilog-ams and verilog-a

i have read that verilog ams is super set of verilog-a , but can some body give me some examples of what features are in ams and not in verilog-a
 

ankitgarg0312 said:
please tell me difference in verilog-ams and verilog-a

i have read that verilog ams is super set of verilog-a , but can some body give me some examples of what features are in ams and not in verilog-a
Click to expand...

I guess verilog ams is a mixed signal language where you can have analog and digital components. VerilogA is analog only.
 

IADanilov said:
Verilog-AMS = Verilog-A + Verilog-D (IEEE 1364 -1995)
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if v-ams also contains verilog-D.
can i synthesize it into gate level netlist??
 

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