Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Verilog AMS problem in mentor graphics

Status
Not open for further replies.

sina.parsnejad

Junior Member level 3
Junior Member level 3
Joined
Aug 21, 2012
Messages
27
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Location
Istanbul, Turkey
Visit site
Activity points
1,410
Hi people
I have been trying to implement the following code which is a current mode comparator into mentor graphics ADMS tool; I have been receiving the following error:
Analog DC computation aborted : no DC convergence found in this design
Is there any problem with my code ? The schematic is also attached.


`include "disciplines.h"
module current_mode_comparator_AMS_Verilog_AMS (OUTplus,OUTnega,INplus,INnega);
//inout OUTplus,OUTnega,INplus,INnega;
//electrical OUTplus,OUTnega,INplus,INnega;
inout INplus,INnega ;
output OUTplus,OUTnega ;
current OUTplus,OUTnega ;
electrical INplus,INnega ;
parameter real positive_amp = 30n ;
parameter real negative_amp = -30n ;
parameter real VIN = 0.6 ;

analog begin
I(OUTplus) <+ positive_amp*tanh(1000*(I(INplus)-I(INnega))) ;
I(OUTnega) <+ negative_amp*tanh(1000*(I(INplus)-I(INnega))) ;
V(INplus,INnega) <+ VIN ;
end

endmodule

Untitled.jpg
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top