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Verilog-AMS in Cadence

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Junior Member level 3
May 9, 2007
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cadence ams

I want to test a model of an op amp in Cadence written in Verilog-AMS. I have compiled the verilog-ams code successfully. I have also created the symbol. But I have found problem when I have tried to put the symbol in a schematic window and simulate a test bench circuit. I think there is a configuration : creating a config view etc..
Please, I need your help: Have you any example explaining how to simulate a test-bench circuit in cadence with a verilog-ams module?
Thank you very much.

verilog ams sample

Open your symbol and save as Spectre view. Try to generate the netlist and see that the symbol is identified in the netlist first including the interface pins.

Probably you need to modify CDF also if it dont work after that also. Open CDF for the symbol and include the pin list in the "Simulation Information" section of the symbol. Later you might need to open a configuration view to tell that you are going to use Verilog instead of any circuits. That you need to specify in the Configuration window. For that you need to use the Hierachy Editor provided in the tools and create a cell view with Hierarchy editor with the same name of schematic where you are going to use that symbol. Actually Hierarchy editor called Cofiguration tells whether you are going to use a schematic, netlist, Verilog, VHDL or Verilog-A for a symbol used in the schematic

Try to follow the steps in that order. Its a bit tricky and you need to follow many Cadence documents probably in the process. But the tool is worth trying for the results and its versatile use. I used it sometime back and I am not sure if the procedure is same in the updated versions.

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