carbon9
Member level 3
Hello,
I'm trying to implement a voltage controlled capacitor in Verilog-A. I tried to use the following script:
However, Verilog compiler does not compile this module. I found this expression in Verilog-A reference manual: "The $table_model() system function has the same restrictions as analog operators. That is, it cannot be used inside of if(), case(), or for() statements unless these statements are controlled by genvar-constant expressions." So, since my analog operator is ddt operator above inside the if statement, it will not compile. However, the manual says something about "genvar" expression. How can I use this to make my module working?
Regards,
I'm trying to implement a voltage controlled capacitor in Verilog-A. I tried to use the following script:
Code:
`include "disciplines.vams"
`include "constants.vams"
module capacitor(p,n);
inout p,n;
electrical p,n;
analog begin
if(V(p,n)>=0 && V(p,n)<2.5)
I(p,n) <+ ddt(V(p,n));
else
I(p,n) <+ 0.1*ddt(p,n);
end
endmoduleHowever, Verilog compiler does not compile this module. I found this expression in Verilog-A reference manual: "The $table_model() system function has the same restrictions as analog operators. That is, it cannot be used inside of if(), case(), or for() statements unless these statements are controlled by genvar-constant expressions." So, since my analog operator is ddt operator above inside the if statement, it will not compile. However, the manual says something about "genvar" expression. How can I use this to make my module working?
Regards,