Verilog A for Divide by n counter ..

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counter veriloga code

hi friends can u give me verilog A code for divide by n counter for giver clock and duty cycle.
 

veriloga counter

This is the code for mod 9 counter


module counter(Q , clock, clear,op);
output op;
output [3:0] Q;
input clock, clear;
reg [3:0] Q;

always @( posedge clock or negedge clear)
begin
if (!clear)
Q = 4'd0;
else if(Q==4'd9)
Q = 4'd0;

else
Q = (Q + 1) ;
end
assign op = (Q==4'd9) ? 1:0;
endmodule
 

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