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[SOLVED] Verilog-A error while using specter via virtuoso

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Bakr.hesham

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Hi,
While running a .Va file using specter, this error happened :
Error(Vacomp-2259) "voltage G1<<--? G2, G, temp;

For this line:
Voltage G1, G2, G, temp;

Can anyone help.
Thanks in advance.
 

Here you are :

Code: 
//`PVA_SKIP_LRM 1
module NFinFETIG_module(G1,G2,G);
inout G1,G2;
output G;
//electrical G1,G2,G;
voltage G1,G2,G, temp;
// parameters use in module
parameter real  p00 =  -0.0001413;
parameter real	p10 =      0.5325;
parameter real	p01 =      0.5151;
parameter real	p20 =      0.4855;
parameter real	p11 =      -1.106;
parameter real	p02 =      0.5964;
parameter real	p30 =      0.1479;
parameter real	p21 =    -0.03365;
parameter real	p12 =     -0.5367;
parameter real	p03 =      -0.095;
parameter real	p40 =       -1.43;
parameter real	p31 =       1.839;
parameter real	p22 =     -0.5109;
parameter real	p13 =       2.242;
parameter real	p04 =       -1.08;
parameter real	p50 =      0.8414;
parameter real	p41 =       -1.07;
parameter real	p32 =      0.2698;
parameter real	p23 =     -0.3414;
parameter real	p14 =     -0.9266;
parameter real	p05 =      0.6336;
//analog $display("nfinfet current G1=%e,G2=%e",I(G1),I(G2));
analog	V(temp) <+ (p00 + p10*V(G1) + p01*V(G2) + p20*pow(V(G1),2) + p11*V(G1)*V(G2) + p02*pow(V(G2),2) + p30*pow(V(G1),3) + p21*pow(V(G1),2)*V(G2)+ p12*V(G1)*pow(V(G2),2) + p03*pow(V(G2),3) + p40*pow(V(G1),4) + p31*pow(V(G1),3)*V(G2) + p22*pow(V(G1),2)*pow(V(G2),2)+ p13*V(G1)*pow(V(G2),3) + p04*pow(V(G2),4) + p50*pow(V(G1),5) + p41*pow(V(G1),4)*V(G2) + p32*pow(V(G1),3)*pow(V(G2),2)+ p23*pow(V(G1),2)*pow(V(G2),3) + p14*V(G1)*pow(V(G2),4) + p05*pow(V(G2),5));
analog  V(G) <+ (V(temp)> 1.2)?(1.1):((V(temp) < -0.3)?(-0.2):(V(temp)));
endmodule
/////////////////////////////////////////////////////////////////////////////////////////////////////
module PFinFETIG_module(G1,G2,G);
inout G1,G2;
output G;
//electrical G1,G2,G;
voltage G1,G2,G,temp;
// main parameters
parameter real    supply = 1;
// parameters use in module
parameter real    p00 =   0.0006506;
parameter real    p10 =      0.4834;
parameter real    p01 =      0.4996;
parameter real    p20 =      -0.524;
parameter real    p11 =      0.7008;
parameter real    p02 =     -0.5111;
parameter real    p30 =      0.4264;
parameter real    p21 =       -1.02;
parameter real    p12 =     -0.6979;
parameter real    p03 =      0.1979;
parameter real    p40 =       1.555;
parameter real    p31 =       -2.48;
parameter real    p22 =      0.5419;
parameter real    p13 =      -1.966;
parameter real    p04 =       1.066;
parameter real    p50 =      0.7802;
parameter real    p41 =      -1.049;
parameter real    p32 =    0.003398;
parameter real    p23 =     0.05535;
parameter real    p14 =     -0.8116;
parameter real    p05 =      0.5151;
analog V(temp) <+ (supply+ p00 + p10*(V(G1)-supply) + p01*(V(G2)-supply) + p20*pow((V(G1)-supply),2) + p11*(V(G1)-supply)*(V(G2)-supply) + p02*pow((V(G2)-supply),2) + p30*pow((V(G1)-supply),3) + p21*pow((V(G1)-supply),2)*(V(G2)-supply)+ p12*(V(G1)-supply)*pow((V(G2)-supply),2) + p03*pow((V(G2)-supply),3) + p40*pow((V(G1)-supply),4) + p31*pow((V(G1)-supply),3)*(V(G2)-supply) + p22*pow((V(G1)-supply),2)*pow((V(G2)-supply),2)+ p13*(V(G1)-supply)*pow((V(G2)-supply),3) + p04*pow((V(G2)-supply),4) + p50*pow((V(G1)-supply),5) + p41*pow((V(G1)-supply),4)*(V(G2)-supply) + p32*pow((V(G1)-supply),3)*pow((V(G2)-supply),2)+ p23*pow((V(G1)-supply),2)*pow((V(G2)-supply),3) + p14*(V(G1)-supply)*pow((V(G2)-supply),4) + p05*pow((V(G2)-supply),5));
analog  V(G) <+ (V(temp)> 1.2)?(1.1):((V(temp) < -0.3)?(-0.2):(V(temp)));
endmodule
 
Last edited by a moderator:

Bakr.hesham said:
While running a .Va file using specter
Click to expand...
Such name's tool does not exist in the world.
Use correct terminology.

Bakr.hesham said:
this error happened :
Error(Vacomp-2259) "voltage G1<<--? G2, G, temp;
Click to expand...
I tested your "NFinFETIG_module(G1,G2,G)" in a simple DC Analysis where DC voltages are fed to G1 and G2, G is open.
There is no problem.

Code: 
module NFinFETIG_module(G1,G2,G);
inout G1,G2;
output G;
//electrical G1,G2,G;
voltage G1,G2,G, temp;

Show us netlist and logfile of Cadence Spectre.
 

ok sorry, can i use google drive ?
https://drive.google.com/open?id=0B6A22GnZewyPdHBVdUZhSW1yQ28

- - - Updated - - -

ok
this is the main file i import to ADL as a model:
Code: 
* IG-FinFET model for 20nm
* November 2012
* site : http:\\ece.ut.ac.ir\dsdlab\

.options post=2 brief

** determine HFIN and GEMOD
.param fin_height=2.8e-008
.param Device_selector=1

** subckt for IGNFinFET **
** nFinFET Drain Front_Gate Back_Gate Source num=1

.include './HP/20nfet.pm'
*.include './LSTP/20nfet.pm'
.hdl "./convertor.va" "NFinFETIG_module"

.subckt nFinFET NVd NVgf NVgb NVs num=1 Lg=24nm 
	* --- Input Capicitance --- *
	M10 NVdn NVgf 0 0 nfet nfin=num l=Lg
	M11 NVdn NVgb 0 0 nfet nfin=num l=Lg
	En1 NVdn 0 NVd  NVs 1
	* ---    Transistors   -----*
	X1 NVgf NVgb SGate NFinFETIG_module 
	M1 NVd SGate NVs 0 nfet nfin= 'num*2' l=Lg
.ends

******************************************************************

** subckt for IGPFinFET **
** pFinFET Drain Front_Gate Back_Gate Source num=1
.include './HP/20pfet.pm'
*.include './LSTP/20pfet.pm'
.hdl "./convertor.va" "PFinFETIG_module"
.param yza = 0.9
vvdd n1 0 yza
.global n1
*** vdd1 must be the same voltage source ***
.subckt pFinFET NVd NVgf NVgb NVs num=1 Lg=24nm
	* --- Input Capicitance --- *
	M10 NVdp NVgf n1 n1 pfet nfin = num l=Lg
	M11 NVdp NVgb n1 n1 pfet nfin = num l=Lg
	En1 NVdp n1 NVd NVs 1
	* ---    Transistors   -----*
	X1 NVgf NVgb SGate PFinFETIG_module supply=yza
	M1 NVd SGate NVs n1 pfet nfin= 'num*2' l=Lg
.ends

the verilog file included:
Code: 
//`PVA_SKIP_LRM 1
module NFinFETIG_module(G1,G2,G);
inout G1,G2;
output G;
//electrical G1,G2,G;
voltage G1,G2,G, temp;
// parameters use in module
parameter real  p00 =  -0.0001413;
parameter real	p10 =      0.5325;
parameter real	p01 =      0.5151;
parameter real	p20 =      0.4855;
parameter real	p11 =      -1.106;
parameter real	p02 =      0.5964;
parameter real	p30 =      0.1479;
parameter real	p21 =    -0.03365;
parameter real	p12 =     -0.5367;
parameter real	p03 =      -0.095;
parameter real	p40 =       -1.43;
parameter real	p31 =       1.839;
parameter real	p22 =     -0.5109;
parameter real	p13 =       2.242;
parameter real	p04 =       -1.08;
parameter real	p50 =      0.8414;
parameter real	p41 =       -1.07;
parameter real	p32 =      0.2698;
parameter real	p23 =     -0.3414;
parameter real	p14 =     -0.9266;
parameter real	p05 =      0.6336;
//analog $display("nfinfet current G1=%e,G2=%e",I(G1),I(G2));
analog	V(temp) <+ (p00 + p10*V(G1) + p01*V(G2) + p20*pow(V(G1),2) + p11*V(G1)*V(G2) + p02*pow(V(G2),2) + p30*pow(V(G1),3) + p21*pow(V(G1),2)*V(G2)+ p12*V(G1)*pow(V(G2),2) + p03*pow(V(G2),3) + p40*pow(V(G1),4) + p31*pow(V(G1),3)*V(G2) + p22*pow(V(G1),2)*pow(V(G2),2)+ p13*V(G1)*pow(V(G2),3) + p04*pow(V(G2),4) + p50*pow(V(G1),5) + p41*pow(V(G1),4)*V(G2) + p32*pow(V(G1),3)*pow(V(G2),2)+ p23*pow(V(G1),2)*pow(V(G2),3) + p14*V(G1)*pow(V(G2),4) + p05*pow(V(G2),5));
analog  V(G) <+ (V(temp)> 1.2)?(1.1):((V(temp) < -0.3)?(-0.2):(V(temp)));
endmodule
/////////////////////////////////////////////////////////////////////////////////////////////////////
module PFinFETIG_module(G1,G2,G);
inout G1,G2;
output G;
//electrical G1,G2,G;
voltage G1,G2,G,temp;
// main parameters
parameter real    supply = 1;
// parameters use in module
parameter real    p00 =   0.0006506;
parameter real    p10 =      0.4834;
parameter real    p01 =      0.4996;
parameter real    p20 =      -0.524;
parameter real    p11 =      0.7008;
parameter real    p02 =     -0.5111;
parameter real    p30 =      0.4264;
parameter real    p21 =       -1.02;
parameter real    p12 =     -0.6979;
parameter real    p03 =      0.1979;
parameter real    p40 =       1.555;
parameter real    p31 =       -2.48;
parameter real    p22 =      0.5419;
parameter real    p13 =      -1.966;
parameter real    p04 =       1.066;
parameter real    p50 =      0.7802;
parameter real    p41 =      -1.049;
parameter real    p32 =    0.003398;
parameter real    p23 =     0.05535;
parameter real    p14 =     -0.8116;
parameter real    p05 =      0.5151;
analog V(temp) <+ (supply+ p00 + p10*(V(G1)-supply) + p01*(V(G2)-supply) + p20*pow((V(G1)-supply),2) + p11*(V(G1)-supply)*(V(G2)-supply) + p02*pow((V(G2)-supply),2) + p30*pow((V(G1)-supply),3) + p21*pow((V(G1)-supply),2)*(V(G2)-supply)+ p12*(V(G1)-supply)*pow((V(G2)-supply),2) + p03*pow((V(G2)-supply),3) + p40*pow((V(G1)-supply),4) + p31*pow((V(G1)-supply),3)*(V(G2)-supply) + p22*pow((V(G1)-supply),2)*pow((V(G2)-supply),2)+ p13*(V(G1)-supply)*pow((V(G2)-supply),3) + p04*pow((V(G2)-supply),4) + p50*pow((V(G1)-supply),5) + p41*pow((V(G1)-supply),4)*(V(G2)-supply) + p32*pow((V(G1)-supply),3)*pow((V(G2)-supply),2)+ p23*pow((V(G1)-supply),2)*pow((V(G2)-supply),3) + p14*(V(G1)-supply)*pow((V(G2)-supply),4) + p05*pow((V(G2)-supply),5));
analog  V(G) <+ (V(temp)> 1.2)?(1.1):((V(temp) < -0.3)?(-0.2):(V(temp)));
endmodule

Spectre output file "errors":
Code: 
Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
Version 14.1.0.138 32bit -- 28 Sep 2014
Copyright (C) 1989-2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.

User: root   Host: localhost.localdomain   HostID: 7F0100   PID: 3434
Memory  available: 904.7285 MB  physical: 1.9854 GB
CPU Type: Intel(R) Core(TM) i3-3110M CPU @ 2.40GHz
          Processor PhysicalID CoreID Frequency Load
              0         0        0     2394.6    15.1
              1         0        1     2394.6     7.6


Simulating `input.scs' on localhost.localdomain at 5:42:49 PM, Tue Nov 22, 2016 (process id: 3434).
Current working directory: /root/simulation/char/spectre/schematic/netlist
Environment variable:
    SPECTRE_DEFAULTS=-E
Command line:
    /usr/local/IC614/MMSIM14/tools.lnx86/bin/spectre input.scs  \
        +escchars +log ../psf/spectre.out +inter=mpsc  \
        +mpssession=spectre0_2894_2 -format sst2 -raw ../psf +lqtimeout  \
        900 -maxw 5 -maxn 5
spectre pid = 3434

Loading /usr/local/IC614/MMSIM14/tools.lnx86/cmi/lib/5.0/libinfineon_sh.so ...
Loading /usr/local/IC614/MMSIM14/tools.lnx86/cmi/lib/5.0/libphilips_o_sh.so ...
Loading /usr/local/IC614/MMSIM14/tools.lnx86/cmi/lib/5.0/libphilips_sh.so ...
Loading /usr/local/IC614/MMSIM14/tools.lnx86/cmi/lib/5.0/libsparam_sh.so ...
Loading /usr/local/IC614/MMSIM14/tools.lnx86/cmi/lib/5.0/libstmodels_sh.so ...
Reading file:  /root/simulation/char/spectre/schematic/netlist/input.scs
Reading file:  /usr/local/IC614/MMSIM14/tools.lnx86/spectre/etc/configs/spectre.cfg
Reading file:  /usr/local/IC614/tsmc13/models/tsmc13rf.scs
Reading file:  /usr/local/IC614/tsmc13/models/RF_12_33_FSG/T013CMSP002_1_1p1/spectre/ResModel.scs
Reading file:  /usr/local/IC614/tsmc13/models/RF_12_33_FSG/T013CMSP002_1_1p1/spectre/rf013.scs
Reading file:  /root/Desktop/IGFinFET_model/IGFinFET_Model_20nm/20IGfet.pm

Warning from spectre during circuit read-in.
    WARNING (SFE-1133): "/root/Desktop/IGFinFET_model/IGFinFET_Model_20nm/20IGfet.pm" 5: Unknown stand-alone option `brief' skipped.

Reading file:  /root/Desktop/IGFinFET_model/IGFinFET_Model_20nm/LSTP/20nfet.pm
Reading file:  /root/Desktop/IGFinFET_model/IGFinFET_Model_20nm/convertor.va

Error found by spectre during AHDL read-in.
    ERROR (VACOMP-2259): "voltage G1<<--? ,G2,G, temp;
"
        "/root/Desktop/IGFinFET_model/IGFinFET_Model_20nm/./convertor.va", line 6: syntax error.
    ERROR (VACOMP-1814): Maximum allowable errors exceeded. Exiting AHDL compilation....
Error found by spectre during AHDL read-in.
    ERROR (SFE-868): "/root/Desktop/IGFinFET_model/IGFinFET_Model_20nm/20IGfet.pm" 17: Unable to open input file `NFinFETIG_module'.
        No such file or directory.

Reading file:  /root/Desktop/IGFinFET_model/IGFinFET_Model_20nm/LSTP/20pfet.pm

Error found by spectre during AHDL read-in.
    ERROR (VACOMP-1814): Maximum allowable errors exceeded. Exiting AHDL compilation....
Error found by spectre during AHDL read-in.
    ERROR (SFE-868): "/root/Desktop/IGFinFET_model/IGFinFET_Model_20nm/20IGfet.pm" 35: Unable to open input file `PFinFETIG_module'.
        No such file or directory.

Time for NDB Parsing: CPU = 1.90371 s, elapsed = 1.91048 s.
Time accumulated: CPU = 1.93371 s, elapsed = 1.91048 s.
Peak resident memory used = 46.9 Mbytes.

Time for parsing: CPU = 0 s, elapsed = 41.008 us.
Time accumulated: CPU = 1.9367 s, elapsed = 1.911 s.
Peak resident memory used = 46.9 Mbytes.

~~~~~~~~~~~~~~~~~~~~~~
Pre-Simulation Summary
~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~

Aggregate audit (5:42:51 PM, Tue Nov 22, 2016):
Time used: CPU = 1.95 s, elapsed = 1.95 s, util. = 100%.
Time spent in licensing: elapsed = 1.71 s, percentage of total = 87.8%.
Peak memory used = 47.2 Mbytes.
Simulation started at: 5:42:49 PM, Tue Nov 22, 2016, ended at: 5:42:51 PM, Tue Nov 22, 2016, with elapsed time (wall clock): 1.95 s.
spectre completes with 5 errors, 1 warning, and 0 notices.
spectre terminated prematurely due to fatal error.
CentOS-2016-11-21-14-50-52.png
 

i cant understand you which file you mean ,i just do the following:
1st -draw the schematic in virtuoso.
2nd-launch the ADL .
3rd-include the model file.
4th-run the simulation .
5th-Simulation results should appears.
that what i do for any simulation in virtuoso , and it works ,but what happens after running this simulation that the shown errors appears .
 

input.scs
Code: 
// Generated for: spectre
// Generated on: Nov 22 17:42:48 2016
// Design library name: hope
// Design cell name: char
// Design view name: schematic
simulator lang=spectre
global 0
include "/usr/local/IC614/tsmc13/tsmc13rf/../models/tsmc13rf.scs"
include "/root/Desktop/IGFinFET_model/IGFinFET_Model_20nm/20IGfet.pm"

// Library name: hope
// Cell name: char
// View name: schematic
I9 (net02   0 0) nfet nfin=1 nf=1 l=2e-08 tfin=1.2e-08
V3 (net02 0) vsource dc=900m type=dc
V1 (net4 0) vsource dc=100m type=dc
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf 
dc dc dev=V3 param=dc start=0 stop=600m write="spectre.dc" oppoint=rawfile \
    maxiters=150 maxsteps=10000 annotate=status 
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts  where=rawfile
save I9d 
saveOptions options save=allpub
 

Bakr.hesham said:
this is the main file i import to ADL as a model:
Click to expand...
Bakr.hesham said:
2nd-launch the ADL .
Click to expand...
What do you mean by "ADL" ?
Use correct terminology.

It seems you can not understand netlists you use at all.

You use mixed netlists of two formats, Spectre and Spice.

Master Netlist is "input.scs" which is Spectre Format.
The following two files are included in "input.scs".
Code: 
include "/usr/local/IC614/tsmc13/tsmc13rf/../models/tsmc13rf.scs"
include "/root/Desktop/IGFinFET_model/IGFinFET_Model_20nm/20IGfet.pm"

"tsmc13rf.scs" is a Spectre Format file.

However "20IGfet.pm" is a Spice Format file.
Three files are included in "20IGfet.pm" by Spice Syntax.
Code: 
.include './HP/20nfet.pm'
.hdl "./convertor.va" "NFinFETIG_module"

.include './HP/20pfet.pm'
.hdl "./convertor.va" "PFinFETIG_module"

You have to add "simulator lang=spice" in head of "20IGfet.pm".

If both "20nfet.pm" and "20pfet.pm" are Spice Syntax, add "simulator lang=spice" in also them.

You have to understand description languages and inclusion's relations of the following files.
Code: 
[B]Reading file:  /root/simulation/char/spectre/schematic/netlist/input.scs
Reading file:  /usr/local/IC614/tsmc13/models/tsmc13rf.scs
Reading file:  /usr/local/IC614/tsmc13/models/RF_12_33_FSG/T013CMSP002_1_1p1/spectre/ResModel.scs
Reading file:  /usr/local/IC614/tsmc13/models/RF_12_33_FSG/T013CMSP002_1_1p1/spectre/rf013.scs

Reading file:  /root/Desktop/IGFinFET_model/IGFinFET_Model_20nm/20IGfet.pm
Reading file:  /root/Desktop/IGFinFET_model/IGFinFET_Model_20nm/convertor.va
Reading file:  /root/Desktop/IGFinFET_model/IGFinFET_Model_20nm/LSTP/20nfet.pm
Reading file:  /root/Desktop/IGFinFET_model/IGFinFET_Model_20nm/LSTP/20pfet.pm
[/B]
 
Last edited:
Thanks for explanation,really it helped me,but i added "simulator lang=spice" nothing changed ,
and while i run "20nfet.pm" (Spice Format) & "tsmc13rf.scs" (Spectre Format) it gives simulation results normally without adding "simulator lang=spice".
But i've changed the path of "20IGfet.pm" to be with "tsmc13rf.scs" and this results shown:
Code: 
Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
Version 14.1.0.138 32bit -- 28 Sep 2014
Copyright (C) 1989-2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.

User: root   Host: localhost.localdomain   HostID: 7F0100   PID: 10215
Memory  available: 783.4419 MB  physical: 1.9854 GB
CPU Type: Intel(R) Core(TM) i3-3110M CPU @ 2.40GHz
          Processor PhysicalID CoreID Frequency Load
              0         0        0     2394.6     0.7
              1         0        1     2394.6     0.5


Simulating `input.scs' on localhost.localdomain at 3:51:29 PM, Fri Nov 25, 2016 (process id: 10215).
Current working directory: /root/simulation/char/spectre/schematic/netlist
Environment variable:
    SPECTRE_DEFAULTS=-E
Command line:
    /usr/local/IC614/MMSIM14/tools.lnx86/bin/spectre input.scs  \
        +escchars +log ../psf/spectre.out +inter=mpsc  \
        +mpssession=spectre1_2945_11 -format sst2 -raw ../psf  \
        +lqtimeout 900 -maxw 5 -maxn 5
spectre pid = 10215

Loading /usr/local/IC614/MMSIM14/tools.lnx86/cmi/lib/5.0/libinfineon_sh.so ...
Loading /usr/local/IC614/MMSIM14/tools.lnx86/cmi/lib/5.0/libphilips_o_sh.so ...
Loading /usr/local/IC614/MMSIM14/tools.lnx86/cmi/lib/5.0/libphilips_sh.so ...
Loading /usr/local/IC614/MMSIM14/tools.lnx86/cmi/lib/5.0/libsparam_sh.so ...
Loading /usr/local/IC614/MMSIM14/tools.lnx86/cmi/lib/5.0/libstmodels_sh.so ...
Reading file:  /root/simulation/char/spectre/schematic/netlist/input.scs
Reading file:  /usr/local/IC614/MMSIM14/tools.lnx86/spectre/etc/configs/spectre.cfg
Reading file:  /usr/local/IC614/tsmc13/models/tsmc13rf.scs
Reading file:  /usr/local/IC614/tsmc13/models/RF_12_33_FSG/T013CMSP002_1_1p1/spectre/ResModel.scs
Reading file:  /usr/local/IC614/tsmc13/models/RF_12_33_FSG/T013CMSP002_1_1p1/spectre/rf013.scs
Reading file:  /home/eslam/Desktop/IGFinFET_model/IGFinFET_Model_20nm/20IGfet.pm

Warning from spectre during circuit read-in.
    WARNING (SFE-1133): "/home/eslam/Desktop/IGFinFET_model/IGFinFET_Model_20nm/20IGfet.pm" 6: Unknown stand-alone option `brief' skipped.

Reading file:  /home/eslam/Desktop/IGFinFET_model/IGFinFET_Model_20nm/LSTP/20nfet.pm
Reading file:  /home/eslam/Desktop/IGFinFET_model/IGFinFET_Model_20nm/convertor.va
Reading file:  /usr/local/IC614/MMSIM14/tools.lnx86/spectre/etc/ahdl/disciplines.vams

Error found by spectre during circuit read-in.
    ERROR (SFE-874): "/home/eslam/Desktop/IGFinFET_model/IGFinFET_Model_20nm/20IGfet.pm" 17: Unexpected quote character """.

Reading file:  /home/eslam/Desktop/IGFinFET_model/IGFinFET_Model_20nm/LSTP/20pfet.pm

Error found by spectre during circuit read-in.
    ERROR (SFE-874): "/home/eslam/Desktop/IGFinFET_model/IGFinFET_Model_20nm/20IGfet.pm" 35: Unexpected quote character """.

Time for NDB Parsing: CPU = 2.50362 s, elapsed = 2.54612 s.
Time accumulated: CPU = 2.54161 s, elapsed = 2.54613 s.
Peak resident memory used = 47.8 Mbytes.

Time for parsing: CPU = 0 s, elapsed = 51.0216 us.
Time accumulated: CPU = 2.54261 s, elapsed = 2.54693 s.
Peak resident memory used = 47.8 Mbytes.

~~~~~~~~~~~~~~~~~~~~~~
Pre-Simulation Summary
~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~

Aggregate audit (3:51:32 PM, Fri Nov 25, 2016):
Time used: CPU = 2.56 s, elapsed = 2.56 s, util. = 99.8%.
Time spent in licensing: elapsed = 2.27 s, percentage of total = 88.5%.
Peak memory used = 48.1 Mbytes.
Simulation started at: 3:51:29 PM, Fri Nov 25, 2016, ended at: 3:51:32 PM, Fri Nov 25, 2016, with elapsed time (wall clock): 2.56 s.
spectre completes with 2 errors, 1 warning, and 0 notices.
spectre terminated prematurely due to fatal error.
 

Correct the followings.
Code: 
Error found by spectre during circuit read-in.
    ERROR (SFE-874): "/home/eslam/Desktop/IGFinFET_model/IGFinFET_Model_20nm/20IGfet.pm" 17: Unexpected quote character """.

Error found by spectre during circuit read-in.
    ERROR (SFE-874): "/home/eslam/Desktop/IGFinFET_model/IGFinFET_Model_20nm/20IGfet.pm" 35: Unexpected quote character """.
 

But i tried to change the syntax nothing changes,the following syntax is the original one.
how can i include models of a .va file in the netlist?

line 17:
Code: 
.hdl "./convertor.va" "NFinFETIG_module"
line 35:
Code: 
.hdl "./convertor.va" "PFinFETIG_module"

error:
Code: 
Error found by spectre during circuit read-in.
    ERROR (SFE-874): "/home/eslam/Desktop/IGFinFET_model/IGFinFET_Model_20nm/20IGfet.pm" 17: Unexpected quote character """.

Error found by spectre during circuit read-in.
    ERROR (SFE-874): "/home/eslam/Desktop/IGFinFET_model/IGFinFET_Model_20nm/20IGfet.pm" 35: Unexpected quote character """.
 

Unfortunately it's also rejected :
line:
Code: 
.hdl './convertor.va' 'NFinFETIG_module'

Error:
Code: 
Error found by spectre during circuit read-in.
    ERROR (SFE-874): "/home/eslam/Desktop/IGFinFET_model/20IGfet.pm" 17: Unexpected quote character "'".

- - - Updated - - -

- - - Updated - - -

no it is the same file :CentOS-2016-11-27-10-44-58.png
 
Last edited:

'convertor.va' have two modules, NFinFETIG_module() and PFinFETIG_module().

Make two new files which include only one module in each them.
I assume new files, 'NFinFETIG_module.va' and 'PFinFETIG_module.va'.

Modify the following lines in '20IGfet.pm'
Code: 
.include './HP/20nfet.pm'
.hdl "./convertor.va" "NFinFETIG_module"

.include './HP/20pfet.pm'
.hdl "./convertor.va" "PFinFETIG_module"

to
Code: 
.include './HP/20nfet.pm'
.hdl './NFinFETIG_module.va'

.include './HP/20pfet.pm'
.hdl './PFinFETIG_module.va'

I think netlist parser of Cadence ADE can not treat HSPICE syntax, .hdl 'file_name' 'module_name' which is relative new syntax in Synopsis HSPICE.
 
Last edited:
Thanks alot for your concern,help and time, the errors gone .
 

Bakr.hesham said:
the errors gone .
Click to expand...
Show us logfile of Cadence Spectre.

If you would like to use "convertor.va" without having two Verilog-A files, try the following.

Make new file, "aho.scs".
Content of "aho.scs" is following.
Code: 
simulator lang=spectre
ahdl_include "/home/eslam/Desktop/IGFinFET_model/convertor.va"

Include "aho.scs" in "input.scs".
Comment out two ".hdl" in "20IGfet.pm".
 
Last edited:
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