Verilog-A Error & PSS analysis

[AMSA84]

Hi guys,

I wrote a small code from a Verilog A tutorial for a comparator.

After implement it, I tried to simulate a simple circuit - Vpulse shaping a triangle wave and a vdc source to see what would appear at the output.

I used a PSS analysis and an error appeared:

**broken link removed**

It says that PSS doesn't support behavioral models with hidden states. Is that true? There is any way to escape from this error and use PSS analysis?

What is hidden states?

 

[culho]

Can you show the comparator code?

 

[erikl]

What is hidden states?

Hidden states are possible circuit states which are not planned to occur in the circuit's special application.

A nice example is a decimal counter made from 4 flip-flops: it could get into 16 states, but just 10 of them are used. If by any event, e.g. a power supply interference or a radiation SEE the circuit falls into such an unplanned (hidden) state, the circuit itself should care to leave it, e.g. by a reset.

Also, a single flip-flop, even a comparator could fall into such a hidden state by such an unplanned event.