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Verilog-a code to latch analog voltages

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Chinmaye

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Dear all,
I am trying to model analog latch in verilog-a but have been unable to do it. The requirement is as follows
It is required to sample an analog value at positive clock cycle of CLK2 and hold the same value even during the negative clock cycle of CLK2.
Any leads??
 

Chinmaye

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@cross() does not allow V() inside it. Hence it cannot be used
 

pancho_hideboo

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@cross() does not allow V() inside it.
Hence it cannot be used
No.
You can not understand Verilog-A at all.

if V(clk2) >=0 aho = V(in);
@cross(V(clk2), -1) aho = V(in);
V(out) <+ aho;
 
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vivekroy

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Dear all,
I am trying to model analog latch in verilog-a but have been unable to do it. The requirement is as follows
It is required to sample an analog value at positive clock cycle of CLK2 and hold the same value even during the negative clock cycle of CLK2.
Any leads??

Look at page 113 of **broken link removed**

Your exact solution is given!!
 

pancho_hideboo

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Look at page 113 of **broken link removed**
Your exact solution is given!!
This is not transparent latch.

For V(Clk2)=High, V(out)=V(in) ; Tranparent
Then V(in) is captured at negative edge of V(Clk2).
V(out) is constant during V(Clk2)=Low ; Hold Mode.
 

vivekroy

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Here you go

Code:
// VerilogA code

`include "constants.vams"
`include "disciplines.vams"

module veriloga_latch(vin,vclk,vout_sampled);
input vin,vclk;
output vout_sampled;
voltage vin, vclk, vout_sampled;
parameter real vdd=1;
real vsample=0;
analog begin
	if (V(vclk)>0.9*vdd) begin
		vsample=V(vin);
	end
	V(vout_sampled) <+ vsample;
	end
	


endmodule

Here is the op:
latch_op.JPG
 
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