Verilog: 8-bit Adder Error: The logic does not match a known FF or Latch template

[Valerius]

As far as I can understand that the hardware required to implement the code below is not supported in Xilinx ISE Web Pack. I'm trying to implement only the functionality of the 8-bit adder using an always block. Here's the code:

module Addr_8bit(Clk, Rst, En, LEDOut  
    );

     input Clk;
     input Rst;
     input En;
     output reg [7:0] LEDOut;

    always @(posedge Clk or posedge Rst) begin
            if(Rst)
                LEDOut <= 8'b00000000;
            if(En)
                LEDOut <= LEDOut + 8'b00000001;
    end
endmodule

The error is on the line where the non-blocking assignment:

LEDOut <= LEDOut + 8'b00000001;

is located.

Particularly it says that:

ERROR:Xst:899 - "Addr_8bit.v" line 33: The logic for <LEDOut> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.

I am trying to make the LEDOut's 8-bit output to correspond to the each single one of 8 LEDs on the BASYS2 FPGA Board(Spartan-3E).

Thank You.

 

[arya.jagadeesh]

As far as I can understand that the hardware required to implement the code below is not supported in Xilinx ISE Web Pack. I'm trying to implement only the functionality of the 8-bit adder using an always block. Here's the code:

module Addr_8bit(Clk, Rst, En, LEDOut  
    );

     input Clk;
     input Rst;
     input En;
     output reg [7:0] LEDOut;

    always @(posedge Clk or posedge Rst) begin
            if(Rst)
                LEDOut <= 8'b00000000;
            if(En)
                LEDOut <= LEDOut + 8'b00000001;
    end
endmodule

The error is on the line where the non-blocking assignment:

LEDOut <= LEDOut + 8'b00000001;

is located.

Particularly it says that:

ERROR:Xst:899 - "Addr_8bit.v" line 33: The logic for <LEDOut> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.

I am trying to make the LEDOut's 8-bit output to correspond to the each single one of 8 LEDs on the BASYS2 FPGA Board(Spartan-3E).

Thank You.

instead of using output signal in assignment ...take one wire or reg and use it it addition ..and finally asign that to output...may be that will work

 

[ads-ee]

Ignore the reply in post #2 it's not the problem and it's not a solution.

Change this:

    always @(posedge Clk or posedge Rst) begin
            if(Rst)
                LEDOut <= 8'b00000000;
            if(En)
                LEDOut <= LEDOut + 8'b00000001;

To this:

always @(posedge Clk or posedge Rst)
  if (Rst)     LEDOut <= 0;
  else if (En) LEDOut <= LEDOut + 1;

Having separate if's for the two situations is not implementable, it suggests two separate FFs that drive the same output signal LEDOut.

BTW camel case code sucks, I had to edit the code three times to fix typos

 

[arya.jagadeesh]

yes...modified code should work...what is happening is ...assignment statement is, you are driving signal
if you are having two drivers to same net it is conflict..instead you can drive it with priority .